Skip to content

Commit 9559772

Browse files
shtaxxxshtaxxx
committed
Bug fix: Fixing the bug in AXI-slave controller that dismisses a read/write request when there is an interval between the asserted timings of arvalid and rready.
1 parent e61f28e commit 9559772

File tree

19 files changed

+545
-120
lines changed

19 files changed

+545
-120
lines changed

‎examples/thread_add_ipxact/test_thread_add_ipxact.py‎

Lines changed: 23 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -731,7 +731,7 @@
731731
(_tmp_5 == 6)? _saxi_resetval_6 :
732732
(_tmp_5 == 7)? _saxi_resetval_7 : 'hx;
733733
reg _saxi_cond_0_1;
734-
assign saxi_wready = _saxi_register_fsm == 2;
734+
assign saxi_wready = _saxi_register_fsm == 3;
735735
reg [32-1:0] th_add;
736736
localparam th_add_init = 0;
737737
reg signed [32-1:0] _th_add_a_0;
@@ -834,28 +834,28 @@
834834
_saxi_register_7 <= _tmp_8;
835835
_saxi_flag_7 <= 0;
836836
end
837-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 0)) begin
837+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 0)) begin
838838
_saxi_register_0 <= saxi_wdata;
839839
end
840-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 1)) begin
840+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 1)) begin
841841
_saxi_register_1 <= saxi_wdata;
842842
end
843-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 2)) begin
843+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 2)) begin
844844
_saxi_register_2 <= saxi_wdata;
845845
end
846-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 3)) begin
846+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 3)) begin
847847
_saxi_register_3 <= saxi_wdata;
848848
end
849-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 4)) begin
849+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 4)) begin
850850
_saxi_register_4 <= saxi_wdata;
851851
end
852-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 5)) begin
852+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 5)) begin
853853
_saxi_register_5 <= saxi_wdata;
854854
end
855-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 6)) begin
855+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 6)) begin
856856
_saxi_register_6 <= saxi_wdata;
857857
end
858-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 7)) begin
858+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 7)) begin
859859
_saxi_register_7 <= saxi_wdata;
860860
end
861861
if((_saxi_register_0 == 1) && (th_add == 2) && 1) begin
@@ -959,6 +959,7 @@
959959
960960
localparam _saxi_register_fsm_1 = 1;
961961
localparam _saxi_register_fsm_2 = 2;
962+
localparam _saxi_register_fsm_3 = 3;
962963
963964
always @(posedge CLK) begin
964965
if(RST) begin
@@ -973,16 +974,26 @@
973974
_saxi_register_fsm <= _saxi_register_fsm_1;
974975
end
975976
if(_tmp_1) begin
976-
_saxi_register_fsm <= _saxi_register_fsm_2;
977+
_saxi_register_fsm <= _saxi_register_fsm_3;
977978
end
978979
end
979980
_saxi_register_fsm_1: begin
980-
if(saxi_rready || !saxi_rvalid) begin
981+
if(saxi_rready && saxi_rvalid) begin
981982
_saxi_register_fsm <= _saxi_register_fsm_init;
982983
end
984+
if((saxi_rready || !saxi_rvalid) && !(saxi_rready && saxi_rvalid)) begin
985+
_saxi_register_fsm <= _saxi_register_fsm_2;
986+
end
983987
end
984988
_saxi_register_fsm_2: begin
985-
_saxi_register_fsm <= _saxi_register_fsm_init;
989+
if(saxi_rready && saxi_rvalid) begin
990+
_saxi_register_fsm <= _saxi_register_fsm_init;
991+
end
992+
end
993+
_saxi_register_fsm_3: begin
994+
if(saxi_wready && saxi_wvalid) begin
995+
_saxi_register_fsm <= _saxi_register_fsm_init;
996+
end
986997
end
987998
endcase
988999
end

‎examples/thread_embedded_verilog_ipcore/test_thread_embedded_verilog_ipxact.py‎

Lines changed: 23 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1289,7 +1289,7 @@
12891289
(_tmp_5 == 6)? _saxi_resetval_6 :
12901290
(_tmp_5 == 7)? _saxi_resetval_7 : 'hx;
12911291
reg _saxi_cond_0_1;
1292-
assign saxi_wready = _saxi_register_fsm == 2;
1292+
assign saxi_wready = _saxi_register_fsm == 3;
12931293
12941294
reg [31:0] sum;
12951295
always @(posedge CLK) begin
@@ -1713,28 +1713,28 @@
17131713
_saxi_register_7 <= _tmp_8;
17141714
_saxi_flag_7 <= 0;
17151715
end
1716-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 0)) begin
1716+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 0)) begin
17171717
_saxi_register_0 <= saxi_wdata;
17181718
end
1719-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 1)) begin
1719+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 1)) begin
17201720
_saxi_register_1 <= saxi_wdata;
17211721
end
1722-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 2)) begin
1722+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 2)) begin
17231723
_saxi_register_2 <= saxi_wdata;
17241724
end
1725-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 3)) begin
1725+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 3)) begin
17261726
_saxi_register_3 <= saxi_wdata;
17271727
end
1728-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 4)) begin
1728+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 4)) begin
17291729
_saxi_register_4 <= saxi_wdata;
17301730
end
1731-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 5)) begin
1731+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 5)) begin
17321732
_saxi_register_5 <= saxi_wdata;
17331733
end
1734-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 6)) begin
1734+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 6)) begin
17351735
_saxi_register_6 <= saxi_wdata;
17361736
end
1737-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 7)) begin
1737+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 7)) begin
17381738
_saxi_register_7 <= saxi_wdata;
17391739
end
17401740
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 1) begin
@@ -1806,6 +1806,7 @@
18061806
18071807
localparam _saxi_register_fsm_1 = 1;
18081808
localparam _saxi_register_fsm_2 = 2;
1809+
localparam _saxi_register_fsm_3 = 3;
18091810
18101811
always @(posedge CLK) begin
18111812
if(RST) begin
@@ -1820,16 +1821,26 @@
18201821
_saxi_register_fsm <= _saxi_register_fsm_1;
18211822
end
18221823
if(_tmp_1) begin
1823-
_saxi_register_fsm <= _saxi_register_fsm_2;
1824+
_saxi_register_fsm <= _saxi_register_fsm_3;
18241825
end
18251826
end
18261827
_saxi_register_fsm_1: begin
1827-
if(saxi_rready || !saxi_rvalid) begin
1828+
if(saxi_rready && saxi_rvalid) begin
18281829
_saxi_register_fsm <= _saxi_register_fsm_init;
18291830
end
1831+
if((saxi_rready || !saxi_rvalid) && !(saxi_rready && saxi_rvalid)) begin
1832+
_saxi_register_fsm <= _saxi_register_fsm_2;
1833+
end
18301834
end
18311835
_saxi_register_fsm_2: begin
1832-
_saxi_register_fsm <= _saxi_register_fsm_init;
1836+
if(saxi_rready && saxi_rvalid) begin
1837+
_saxi_register_fsm <= _saxi_register_fsm_init;
1838+
end
1839+
end
1840+
_saxi_register_fsm_3: begin
1841+
if(saxi_wready && saxi_wvalid) begin
1842+
_saxi_register_fsm <= _saxi_register_fsm_init;
1843+
end
18331844
end
18341845
endcase
18351846
end

‎examples/thread_ipxact/test_thread_ipxact.py‎

Lines changed: 19 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -660,7 +660,7 @@
660660
(_tmp_5 == 2)? _saxi_resetval_2 :
661661
(_tmp_5 == 3)? _saxi_resetval_3 : 'hx;
662662
reg _saxi_cond_0_1;
663-
assign saxi_wready = _saxi_register_fsm == 2;
663+
assign saxi_wready = _saxi_register_fsm == 3;
664664
reg [32-1:0] th_blink;
665665
localparam th_blink_init = 0;
666666
reg signed [32-1:0] _th_blink_size_0;
@@ -736,16 +736,16 @@
736736
_saxi_register_3 <= _tmp_8;
737737
_saxi_flag_3 <= 0;
738738
end
739-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 0)) begin
739+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 0)) begin
740740
_saxi_register_0 <= saxi_wdata;
741741
end
742-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 1)) begin
742+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 1)) begin
743743
_saxi_register_1 <= saxi_wdata;
744744
end
745-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 2)) begin
745+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 2)) begin
746746
_saxi_register_2 <= saxi_wdata;
747747
end
748-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 3)) begin
748+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 3)) begin
749749
_saxi_register_3 <= saxi_wdata;
750750
end
751751
if((_saxi_register_0 == 1) && (th_blink == 2) && 1) begin
@@ -801,6 +801,7 @@
801801
802802
localparam _saxi_register_fsm_1 = 1;
803803
localparam _saxi_register_fsm_2 = 2;
804+
localparam _saxi_register_fsm_3 = 3;
804805
805806
always @(posedge CLK) begin
806807
if(RST) begin
@@ -815,16 +816,26 @@
815816
_saxi_register_fsm <= _saxi_register_fsm_1;
816817
end
817818
if(_tmp_1) begin
818-
_saxi_register_fsm <= _saxi_register_fsm_2;
819+
_saxi_register_fsm <= _saxi_register_fsm_3;
819820
end
820821
end
821822
_saxi_register_fsm_1: begin
822-
if(saxi_rready || !saxi_rvalid) begin
823+
if(saxi_rready && saxi_rvalid) begin
823824
_saxi_register_fsm <= _saxi_register_fsm_init;
824825
end
826+
if((saxi_rready || !saxi_rvalid) && !(saxi_rready && saxi_rvalid)) begin
827+
_saxi_register_fsm <= _saxi_register_fsm_2;
828+
end
825829
end
826830
_saxi_register_fsm_2: begin
827-
_saxi_register_fsm <= _saxi_register_fsm_init;
831+
if(saxi_rready && saxi_rvalid) begin
832+
_saxi_register_fsm <= _saxi_register_fsm_init;
833+
end
834+
end
835+
_saxi_register_fsm_3: begin
836+
if(saxi_wready && saxi_wvalid) begin
837+
_saxi_register_fsm <= _saxi_register_fsm_init;
838+
end
828839
end
829840
endcase
830841
end

‎examples/thread_memcpy_ipxact/test_thread_memcpy_ipxact.py‎

Lines changed: 23 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1286,7 +1286,7 @@
12861286
(_tmp_5 == 6)? _saxi_resetval_6 :
12871287
(_tmp_5 == 7)? _saxi_resetval_7 : 'hx;
12881288
reg _saxi_cond_0_1;
1289-
assign saxi_wready = _saxi_register_fsm == 2;
1289+
assign saxi_wready = _saxi_register_fsm == 3;
12901290
reg [32-1:0] th_memcpy;
12911291
localparam th_memcpy_init = 0;
12921292
reg signed [32-1:0] _th_memcpy_copy_bytes_0;
@@ -1696,28 +1696,28 @@
16961696
_saxi_register_7 <= _tmp_8;
16971697
_saxi_flag_7 <= 0;
16981698
end
1699-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 0)) begin
1699+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 0)) begin
17001700
_saxi_register_0 <= saxi_wdata;
17011701
end
1702-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 1)) begin
1702+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 1)) begin
17031703
_saxi_register_1 <= saxi_wdata;
17041704
end
1705-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 2)) begin
1705+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 2)) begin
17061706
_saxi_register_2 <= saxi_wdata;
17071707
end
1708-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 3)) begin
1708+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 3)) begin
17091709
_saxi_register_3 <= saxi_wdata;
17101710
end
1711-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 4)) begin
1711+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 4)) begin
17121712
_saxi_register_4 <= saxi_wdata;
17131713
end
1714-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 5)) begin
1714+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 5)) begin
17151715
_saxi_register_5 <= saxi_wdata;
17161716
end
1717-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 6)) begin
1717+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 6)) begin
17181718
_saxi_register_6 <= saxi_wdata;
17191719
end
1720-
if((_saxi_register_fsm == 2) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 7)) begin
1720+
if((_saxi_register_fsm == 3) && (saxi_wready && saxi_wvalid) && (_tmp_5 == 7)) begin
17211721
_saxi_register_7 <= saxi_wdata;
17221722
end
17231723
if((_saxi_register_0 == 1) && (th_memcpy == 2) && 1) begin
@@ -1789,6 +1789,7 @@
17891789
17901790
localparam _saxi_register_fsm_1 = 1;
17911791
localparam _saxi_register_fsm_2 = 2;
1792+
localparam _saxi_register_fsm_3 = 3;
17921793
17931794
always @(posedge CLK) begin
17941795
if(RST) begin
@@ -1803,16 +1804,26 @@
18031804
_saxi_register_fsm <= _saxi_register_fsm_1;
18041805
end
18051806
if(_tmp_1) begin
1806-
_saxi_register_fsm <= _saxi_register_fsm_2;
1807+
_saxi_register_fsm <= _saxi_register_fsm_3;
18071808
end
18081809
end
18091810
_saxi_register_fsm_1: begin
1810-
if(saxi_rready || !saxi_rvalid) begin
1811+
if(saxi_rready && saxi_rvalid) begin
18111812
_saxi_register_fsm <= _saxi_register_fsm_init;
18121813
end
1814+
if((saxi_rready || !saxi_rvalid) && !(saxi_rready && saxi_rvalid)) begin
1815+
_saxi_register_fsm <= _saxi_register_fsm_2;
1816+
end
18131817
end
18141818
_saxi_register_fsm_2: begin
1815-
_saxi_register_fsm <= _saxi_register_fsm_init;
1819+
if(saxi_rready && saxi_rvalid) begin
1820+
_saxi_register_fsm <= _saxi_register_fsm_init;
1821+
end
1822+
end
1823+
_saxi_register_fsm_3: begin
1824+
if(saxi_wready && saxi_wvalid) begin
1825+
_saxi_register_fsm <= _saxi_register_fsm_init;
1826+
end
18161827
end
18171828
endcase
18181829
end

0 commit comments

Comments
 (0)