SubstreamMultiCycle is improved. Reduction operators and ReadRAM/WriteRAM are supported in SubstreamMultiCycle.

Author: shtaxxx

tests/extension/thread_/stream_axi_stream/test_thread_stream_axi_stream.py

@@ -191,7 +191,9 @@
 
   reg _mystream_stream_ivalid;
   wire _mystream_stream_oready;
-  assign _mystream_stream_oready = 1;
+  wire _mystream_stream_internal_oready;
+  assign _mystream_stream_internal_oready = 1;
+  assign _mystream_stream_oready = _mystream_stream_internal_oready;
   reg [32-1:0] _mystream_fsm;
   localparam _mystream_fsm_init = 0;
   wire _mystream_run_flag;
@@ -1103,13 +1105,13 @@
       _mystream_source_stop <= 0;
       _mystream_stream_ivalid <= 0;
     end else begin
-      if(_tmp_46 && _mystream_stream_oready) begin
+      if(_mystream_stream_oready && _tmp_46) begin
         _mystream_stream_ivalid <= 1;
       end 
       if(_mystream_stream_oready) begin
         _mystream_source_stop <= 0;
       end 
-      if(_tmp_49 && _mystream_stream_oready) begin
+      if(_mystream_stream_oready && _tmp_49) begin
         _mystream_stream_ivalid <= 0;
       end 
       case(_mystream_fsm)

tests/extension/thread_/stream_axi_stream_async/test_thread_stream_axi_stream_async.py

@@ -191,7 +191,9 @@
 
   reg _mystream_stream_ivalid;
   wire _mystream_stream_oready;
-  assign _mystream_stream_oready = 1;
+  wire _mystream_stream_internal_oready;
+  assign _mystream_stream_internal_oready = 1;
+  assign _mystream_stream_oready = _mystream_stream_internal_oready;
   reg [32-1:0] _mystream_fsm;
   localparam _mystream_fsm_init = 0;
   wire _mystream_run_flag;
@@ -1103,13 +1105,13 @@
       _mystream_source_stop <= 0;
       _mystream_stream_ivalid <= 0;
     end else begin
-      if(_tmp_46 && _mystream_stream_oready) begin
+      if(_mystream_stream_oready && _tmp_46) begin
         _mystream_stream_ivalid <= 1;
       end 
       if(_mystream_stream_oready) begin
         _mystream_source_stop <= 0;
       end 
-      if(_tmp_49 && _mystream_stream_oready) begin
+      if(_mystream_stream_oready && _tmp_49) begin
         _mystream_stream_ivalid <= 0;
       end 
       case(_mystream_fsm)

tests/extension/thread_/stream_counter_stall/thread_stream_counter_stall.py

@@ -44,7 +44,7 @@ def mkLed():
         count.inc()
     )
 
-    util.add_disable_cond(strm.stream_oready, 1, count == 0)
+    util.add_disable_cond(strm.oready, 1, count == 0)
 
     def comp_stream(size, offset):
         strm.set_source('a', ram_a, offset, size)

tests/extension/thread_/stream_linebuffer2d_2_stall/thread_stream_linebuffer2d_2_stall.py

@@ -64,7 +64,7 @@ def mkLed():
         count.inc()
     )
 
-    util.add_disable_cond(strm.stream_oready, 1, count == 0)
+    util.add_disable_cond(strm.oready, 1, count == 0)
 
     # for sequential
     ram_bufs = [vthread.RAM(m, 'ram_buf' + str(i), clk, rst, datawidth, addrwidth)

tests/extension/thread_/stream_linebuffer2d_stall/thread_stream_linebuffer2d_stall.py

@@ -58,7 +58,7 @@ def mkLed():
         count.inc()
     )
 
-    util.add_disable_cond(strm.stream_oready, 1, count == 0)
+    util.add_disable_cond(strm.oready, 1, count == 0)
 
     def comp_stream(width, height, offset):
         strm.set_source('dummy_src', ram_dummy_src, offset, width * height * 2 * 2)

tests/extension/thread_/stream_linebuffer3d_stall/thread_stream_linebuffer3d_stall.py

@@ -61,7 +61,7 @@ def mkLed():
         count.inc()
     )
 
-    util.add_disable_cond(strm.stream_oready, 1, count == 0)
+    util.add_disable_cond(strm.oready, 1, count == 0)
 
     def comp_stream(channel, width, height, offset):
         strm.set_source('dummy_src', ram_dummy_src, offset, channel * width * height * 2 * 2)

tests/extension/thread_/stream_multipattern_stall/thread_stream_multipattern_stall.py

@@ -53,7 +53,7 @@ def mkLed():
         count.inc()
     )
 
-    util.add_disable_cond(strm.stream_oready, 1, count == 0)
+    util.add_disable_cond(strm.oready, 1, count == 0)
 
     def comp_stream():
         strm.set_source_multipattern('a', ram_a, offsets, patterns)

tests/extension/thread_/stream_ram_external_ports/test_thread_stream_ram_external_ports.py

@@ -161,7 +161,9 @@
   assign saxi_wready = _saxi_register_fsm == 2;
   reg _mystream_stream_ivalid;
   wire _mystream_stream_oready;
-  assign _mystream_stream_oready = 1;
+  wire _mystream_stream_internal_oready;
+  assign _mystream_stream_internal_oready = 1;
+  assign _mystream_stream_oready = _mystream_stream_internal_oready;
   reg [32-1:0] _mystream_fsm;
   localparam _mystream_fsm_init = 0;
   wire _mystream_run_flag;
@@ -734,13 +736,13 @@
       _mystream_source_stop <= 0;
       _mystream_stream_ivalid <= 0;
     end else begin
-      if(_tmp_28 && _mystream_stream_oready) begin
+      if(_mystream_stream_oready && _tmp_28) begin
         _mystream_stream_ivalid <= 1;
       end 
       if(_mystream_stream_oready) begin
         _mystream_source_stop <= 0;
       end 
-      if(_tmp_31 && _mystream_stream_oready) begin
+      if(_mystream_stream_oready && _tmp_31) begin
         _mystream_stream_ivalid <= 0;
       end 
       case(_mystream_fsm)

tests/extension/thread_/stream_read_modify_write/thread_stream_read_modify_write.py

@@ -85,7 +85,7 @@ def comp(size):
 
         # sequential
         offset = size * 4
-        myaxi.dma_read(ram_a, offset, 0, size * 2)
+        myaxi.dma_read(ram_a, offset, 0, size)
         comp_sequential(numbins, size, offset)
         myaxi.dma_write(ram_b, offset, 1024 * 2, numbins)
 

tests/extension/thread_/stream_read_modify_write_stall/thread_stream_read_modify_write_stall.py

@@ -47,7 +47,7 @@ def mkLed():
         count.inc()
     )
 
-    util.add_disable_cond(strm.stream_oready, 1, count == 0)
+    util.add_disable_cond(strm.oready, 1, count == 0)
 
     def comp_stream(numbins, size, offset):
         for i in range(numbins):