Merge branch 'feature_multicycle' into develop

Author: shtaxxx

examples/thread_stream_axi_stream_fifo/test_thread_stream_axi_stream_fifo.py

@@ -211,14 +211,16 @@
   reg _ivalid_33;
   reg _ivalid_34;
   reg _ivalid_35;
-  reg _ivalid_36;
-  reg _ivalid_37;
-  assign ovalid = _ivalid_37;
+  assign ovalid = _ivalid_35;
   assign iready = oready;
-  reg signed [32-1:0] _divide_div_ldata_2;
-  reg signed [32-1:0] _divide_div_rdata_2;
-  reg [32-1:0] _divide_div_abs_ldata_2;
-  reg [32-1:0] _divide_div_abs_rdata_2;
+  wire signed [32-1:0] _divide_div_ldata_2;
+  wire signed [32-1:0] _divide_div_rdata_2;
+  assign _divide_div_ldata_2 = xdata;
+  assign _divide_div_rdata_2 = ydata;
+  wire [32-1:0] _divide_div_abs_ldata_2;
+  wire [32-1:0] _divide_div_abs_rdata_2;
+  assign _divide_div_abs_ldata_2 = (_divide_div_ldata_2[31] == 0)? _divide_div_ldata_2 : ~_divide_div_ldata_2 + 1;
+  assign _divide_div_abs_rdata_2 = (_divide_div_rdata_2[31] == 0)? _divide_div_rdata_2 : ~_divide_div_rdata_2 + 1;
   wire _divide_div_osign_2;
   wire signed [32-1:0] _divide_div_abs_odata_2;
   reg signed [32-1:0] _divide_div_odata_2;
@@ -257,9 +259,7 @@
   reg _divide_div_sign_tmp_30_2;
   reg _divide_div_sign_tmp_31_2;
   reg _divide_div_sign_tmp_32_2;
-  reg _divide_div_sign_tmp_33_2;
-  reg _divide_div_sign_tmp_34_2;
-  assign _divide_div_osign_2 = _divide_div_sign_tmp_34_2;
+  assign _divide_div_osign_2 = _divide_div_sign_tmp_32_2;
   wire _divide_div_update_2;
   assign _divide_div_update_2 = oready;
 
@@ -317,12 +317,6 @@
       _ivalid_33 <= 0;
       _ivalid_34 <= 0;
       _ivalid_35 <= 0;
-      _ivalid_36 <= 0;
-      _ivalid_37 <= 0;
-      _divide_div_ldata_2 <= 0;
-      _divide_div_rdata_2 <= 0;
-      _divide_div_abs_ldata_2 <= 0;
-      _divide_div_abs_rdata_2 <= 0;
       _divide_div_odata_2 <= 0;
       _divide_div_sign_tmp_0_2 <= 0;
       _divide_div_sign_tmp_1_2 <= 0;
@@ -357,8 +351,6 @@
       _divide_div_sign_tmp_30_2 <= 0;
       _divide_div_sign_tmp_31_2 <= 0;
       _divide_div_sign_tmp_32_2 <= 0;
-      _divide_div_sign_tmp_33_2 <= 0;
-      _divide_div_sign_tmp_34_2 <= 0;
     end else begin
       if(oready) begin
         _ivalid_1 <= ivalid;
@@ -465,24 +457,6 @@
       if(oready) begin
         _ivalid_35 <= _ivalid_34;
       end 
-      if(oready) begin
-        _ivalid_36 <= _ivalid_35;
-      end 
-      if(oready) begin
-        _ivalid_37 <= _ivalid_36;
-      end 
-      if(oready) begin
-        _divide_div_ldata_2 <= xdata;
-      end 
-      if(oready) begin
-        _divide_div_rdata_2 <= ydata;
-      end 
-      if(oready) begin
-        _divide_div_abs_ldata_2 <= (_divide_div_ldata_2[31] == 0)? _divide_div_ldata_2 : ~_divide_div_ldata_2 + 1;
-      end 
-      if(oready) begin
-        _divide_div_abs_rdata_2 <= (_divide_div_rdata_2[31] == 0)? _divide_div_rdata_2 : ~_divide_div_rdata_2 + 1;
-      end 
       if(oready) begin
         _divide_div_odata_2 <= (_divide_div_osign_2 == 0)? _divide_div_abs_odata_2 : ~_divide_div_abs_odata_2 + 1;
       end 
@@ -585,12 +559,6 @@
       if(oready) begin
         _divide_div_sign_tmp_32_2 <= _divide_div_sign_tmp_31_2;
       end 
-      if(oready) begin
-        _divide_div_sign_tmp_33_2 <= _divide_div_sign_tmp_32_2;
-      end 
-      if(oready) begin
-        _divide_div_sign_tmp_34_2 <= _divide_div_sign_tmp_33_2;
-      end 
     end
   end
 

tests/extension/stream_/div_validready/test_stream_div_validready.py

@@ -197,33 +197,33 @@
     if(RST) begin
       _plus_data_3 <= 0;
       __delay_data_10__variable_2 <= 0;
-      _reduceadd_data_4 <= 1'sd0;
       _reduceadd_count_4 <= 0;
       _reduceadd_prev_count_max_4 <= 0;
-      _pulse_data_7 <= 1'sd0;
+      _reduceadd_data_4 <= 1'sd0;
       _pulse_count_7 <= 0;
       _pulse_prev_count_max_7 <= 0;
+      _pulse_data_7 <= 1'sd0;
     end else begin
       _plus_data_3 <= xdata + ydata;
       __delay_data_10__variable_2 <= edata;
-      if(__delay_data_10__variable_2) begin
-        _reduceadd_data_4 <= _reduceadd_current_data_4 + _plus_data_3;
-      end 
       if(__delay_data_10__variable_2) begin
         _reduceadd_count_4 <= (_reduceadd_current_count_4 >= 5'sd8 - 1)? 0 : _reduceadd_current_count_4 + 1;
       end 
       if(__delay_data_10__variable_2) begin
         _reduceadd_prev_count_max_4 <= _reduceadd_current_count_4 >= 5'sd8 - 1;
       end 
       if(__delay_data_10__variable_2) begin
-        _pulse_data_7 <= _pulse_current_count_7 >= 5'sd8 - 1;
+        _reduceadd_data_4 <= _reduceadd_current_data_4 + _plus_data_3;
       end 
       if(__delay_data_10__variable_2) begin
         _pulse_count_7 <= (_pulse_current_count_7 >= 5'sd8 - 1)? 0 : _pulse_current_count_7 + 1;
       end 
       if(__delay_data_10__variable_2) begin
         _pulse_prev_count_max_7 <= _pulse_current_count_7 >= 5'sd8 - 1;
       end 
+      if(__delay_data_10__variable_2) begin
+        _pulse_data_7 <= _pulse_current_count_7 >= 5'sd8 - 1;
+      end 
     end
   end
 

tests/extension/stream_/reduceadd/test_stream_reduceadd.py

@@ -210,34 +210,34 @@
       _ivalid_1 <= 0;
       _ivalid_2 <= 0;
       _plus_data_2 <= 0;
-      _reduceadd_data_3 <= 1'sd0;
       _reduceadd_count_3 <= 0;
       _reduceadd_prev_count_max_3 <= 0;
-      _pulse_data_6 <= 1'sd0;
+      _reduceadd_data_3 <= 1'sd0;
       _pulse_count_6 <= 0;
       _pulse_prev_count_max_6 <= 0;
+      _pulse_data_6 <= 1'sd0;
     end else begin
       _ivalid_1 <= ivalid;
       _ivalid_2 <= _ivalid_1;
       _plus_data_2 <= xdata + ydata;
-      if(_ivalid_1) begin
-        _reduceadd_data_3 <= _reduceadd_current_data_3 + _plus_data_2;
-      end 
       if(_ivalid_1) begin
         _reduceadd_count_3 <= (_reduceadd_current_count_3 >= 5'sd8 - 1)? 0 : _reduceadd_current_count_3 + 1;
       end 
       if(_ivalid_1) begin
         _reduceadd_prev_count_max_3 <= _reduceadd_current_count_3 >= 5'sd8 - 1;
       end 
       if(_ivalid_1) begin
-        _pulse_data_6 <= _pulse_current_count_6 >= 5'sd8 - 1;
+        _reduceadd_data_3 <= _reduceadd_current_data_3 + _plus_data_2;
       end 
       if(_ivalid_1) begin
         _pulse_count_6 <= (_pulse_current_count_6 >= 5'sd8 - 1)? 0 : _pulse_current_count_6 + 1;
       end 
       if(_ivalid_1) begin
         _pulse_prev_count_max_6 <= _pulse_current_count_6 >= 5'sd8 - 1;
       end 
+      if(_ivalid_1) begin
+        _pulse_data_6 <= _pulse_current_count_6 >= 5'sd8 - 1;
+      end 
     end
   end
 

tests/extension/stream_/reduceadd_valid/test_stream_reduceadd_valid.py

@@ -231,12 +231,12 @@
       _ivalid_1 <= 0;
       _ivalid_2 <= 0;
       _plus_data_2 <= 0;
-      _reduceadd_data_3 <= 1'sd0;
       _reduceadd_count_3 <= 0;
       _reduceadd_prev_count_max_3 <= 0;
-      _pulse_data_6 <= 1'sd0;
+      _reduceadd_data_3 <= 1'sd0;
       _pulse_count_6 <= 0;
       _pulse_prev_count_max_6 <= 0;
+      _pulse_data_6 <= 1'sd0;
     end else begin
       if(oready) begin
         _ivalid_1 <= ivalid;
@@ -247,24 +247,24 @@
       if(oready) begin
         _plus_data_2 <= xdata + ydata;
       end 
-      if(_ivalid_1 && oready) begin
-        _reduceadd_data_3 <= _reduceadd_current_data_3 + _plus_data_2;
-      end 
       if(_ivalid_1 && oready) begin
         _reduceadd_count_3 <= (_reduceadd_current_count_3 >= 5'sd8 - 1)? 0 : _reduceadd_current_count_3 + 1;
       end 
       if(_ivalid_1 && oready) begin
         _reduceadd_prev_count_max_3 <= _reduceadd_current_count_3 >= 5'sd8 - 1;
       end 
       if(_ivalid_1 && oready) begin
-        _pulse_data_6 <= _pulse_current_count_6 >= 5'sd8 - 1;
+        _reduceadd_data_3 <= _reduceadd_current_data_3 + _plus_data_2;
       end 
       if(_ivalid_1 && oready) begin
         _pulse_count_6 <= (_pulse_current_count_6 >= 5'sd8 - 1)? 0 : _pulse_current_count_6 + 1;
       end 
       if(_ivalid_1 && oready) begin
         _pulse_prev_count_max_6 <= _pulse_current_count_6 >= 5'sd8 - 1;
       end 
+      if(_ivalid_1 && oready) begin
+        _pulse_data_6 <= _pulse_current_count_6 >= 5'sd8 - 1;
+      end 
     end
   end
 

tests/extension/stream_/reduceadd_validready/test_stream_reduceadd_validready.py

@@ -202,12 +202,8 @@
   reg signed [32-1:0] __delay_data_22__delay_21__delay_20__variable_5;
   reg signed [32-1:0] __delay_data_23__delay_22__delay_21__delay_20__variable_5;
   reg signed [32-1:0] __delay_data_24__delay_23__delay_22__delay_21____variable_5;
-  reg signed [32-1:0] __delay_data_25__delay_24__delay_23__delay_22____variable_5;
-  reg signed [32-1:0] __delay_data_26__delay_25__delay_24__delay_23____variable_5;
-  reg signed [32-1:0] __delay_data_27__delay_26__delay_25__delay_24____variable_5;
-  reg signed [32-1:0] __delay_data_28__delay_27__delay_26__delay_25____variable_5;
-  reg signed [32-1:0] __substreamoutput_data_11;
-  reg signed [32-1:0] __delay_data_29__delay_28__delay_27__delay_26____variable_5;
+  wire signed [32-1:0] __substreamoutput_data_11;
+  assign __substreamoutput_data_11 = cdata;
   reg signed [32-1:0] _reduceadd_data_12;
   reg [6-1:0] _reduceadd_count_12;
   reg _reduceadd_prev_count_max_12;
@@ -227,9 +223,9 @@
   wire [1-1:0] _pulse_current_data_15;
   assign _pulse_current_data_15 = (_pulse_reset_cond_15)? 1'sd0 : _pulse_data_15;
   reg signed [32-1:0] _plus_data_18;
-  reg [1-1:0] __delay_data_30_pulse_15;
+  reg [1-1:0] __delay_data_25_pulse_15;
   assign zdata = _plus_data_18;
-  assign vdata = __delay_data_30_pulse_15;
+  assign vdata = __delay_data_25_pulse_15;
 
   always @(posedge CLK) begin
     if(RST) begin
@@ -253,20 +249,14 @@
       __delay_data_22__delay_21__delay_20__variable_5 <= 0;
       __delay_data_23__delay_22__delay_21__delay_20__variable_5 <= 0;
       __delay_data_24__delay_23__delay_22__delay_21____variable_5 <= 0;
-      __delay_data_25__delay_24__delay_23__delay_22____variable_5 <= 0;
-      __delay_data_26__delay_25__delay_24__delay_23____variable_5 <= 0;
-      __delay_data_27__delay_26__delay_25__delay_24____variable_5 <= 0;
-      __delay_data_28__delay_27__delay_26__delay_25____variable_5 <= 0;
-      __substreamoutput_data_11 <= 0;
-      __delay_data_29__delay_28__delay_27__delay_26____variable_5 <= 0;
-      _reduceadd_data_12 <= 1'sd0;
       _reduceadd_count_12 <= 0;
       _reduceadd_prev_count_max_12 <= 0;
-      _pulse_data_15 <= 1'sd0;
+      _reduceadd_data_12 <= 1'sd0;
       _pulse_count_15 <= 0;
       _pulse_prev_count_max_15 <= 0;
+      _pulse_data_15 <= 1'sd0;
       _plus_data_18 <= 0;
-      __delay_data_30_pulse_15 <= 0;
+      __delay_data_25_pulse_15 <= 0;
     end else begin
       _plus_data_6 <= xdata + 2'sd1;
       _plus_data_8 <= ydata + 3'sd2;
@@ -275,32 +265,26 @@
       __delay_data_22__delay_21__delay_20__variable_5 <= __delay_data_21__delay_20__variable_5;
       __delay_data_23__delay_22__delay_21__delay_20__variable_5 <= __delay_data_22__delay_21__delay_20__variable_5;
       __delay_data_24__delay_23__delay_22__delay_21____variable_5 <= __delay_data_23__delay_22__delay_21__delay_20__variable_5;
-      __delay_data_25__delay_24__delay_23__delay_22____variable_5 <= __delay_data_24__delay_23__delay_22__delay_21____variable_5;
-      __delay_data_26__delay_25__delay_24__delay_23____variable_5 <= __delay_data_25__delay_24__delay_23__delay_22____variable_5;
-      __delay_data_27__delay_26__delay_25__delay_24____variable_5 <= __delay_data_26__delay_25__delay_24__delay_23____variable_5;
-      __delay_data_28__delay_27__delay_26__delay_25____variable_5 <= __delay_data_27__delay_26__delay_25__delay_24____variable_5;
-      __substreamoutput_data_11 <= cdata;
-      __delay_data_29__delay_28__delay_27__delay_26____variable_5 <= __delay_data_28__delay_27__delay_26__delay_25____variable_5;
-      if(__delay_data_29__delay_28__delay_27__delay_26____variable_5) begin
-        _reduceadd_data_12 <= _reduceadd_current_data_12 + __substreamoutput_data_11;
-      end 
-      if(__delay_data_29__delay_28__delay_27__delay_26____variable_5) begin
+      if(__delay_data_24__delay_23__delay_22__delay_21____variable_5) begin
         _reduceadd_count_12 <= (_reduceadd_current_count_12 >= 5'sd8 - 1)? 0 : _reduceadd_current_count_12 + 1;
       end 
-      if(__delay_data_29__delay_28__delay_27__delay_26____variable_5) begin
+      if(__delay_data_24__delay_23__delay_22__delay_21____variable_5) begin
         _reduceadd_prev_count_max_12 <= _reduceadd_current_count_12 >= 5'sd8 - 1;
       end 
-      if(__delay_data_29__delay_28__delay_27__delay_26____variable_5) begin
-        _pulse_data_15 <= _pulse_current_count_15 >= 5'sd8 - 1;
+      if(__delay_data_24__delay_23__delay_22__delay_21____variable_5) begin
+        _reduceadd_data_12 <= _reduceadd_current_data_12 + __substreamoutput_data_11;
       end 
-      if(__delay_data_29__delay_28__delay_27__delay_26____variable_5) begin
+      if(__delay_data_24__delay_23__delay_22__delay_21____variable_5) begin
         _pulse_count_15 <= (_pulse_current_count_15 >= 5'sd8 - 1)? 0 : _pulse_current_count_15 + 1;
       end 
-      if(__delay_data_29__delay_28__delay_27__delay_26____variable_5) begin
+      if(__delay_data_24__delay_23__delay_22__delay_21____variable_5) begin
         _pulse_prev_count_max_15 <= _pulse_current_count_15 >= 5'sd8 - 1;
       end 
+      if(__delay_data_24__delay_23__delay_22__delay_21____variable_5) begin
+        _pulse_data_15 <= _pulse_current_count_15 >= 5'sd8 - 1;
+      end 
       _plus_data_18 <= _reduceadd_data_12 + 11'sd1000;
-      __delay_data_30_pulse_15 <= _pulse_data_15;
+      __delay_data_25_pulse_15 <= _pulse_data_15;
     end
   end
 
@@ -347,22 +331,14 @@
   reg signed [32-1:0] _b;
   wire signed [64-1:0] _mul;
   reg signed [64-1:0] _pipe_mul0;
-  reg signed [64-1:0] _pipe_mul1;
-  reg signed [64-1:0] _pipe_mul2;
-  reg signed [64-1:0] _pipe_mul3;
-  reg signed [64-1:0] _pipe_mul4;
   assign _mul = _a * _b;
-  assign c = _pipe_mul4;
+  assign c = _pipe_mul0;
 
   always @(posedge CLK) begin
     if(update) begin
       _a <= a;
       _b <= b;
       _pipe_mul0 <= _mul;
-      _pipe_mul1 <= _pipe_mul0;
-      _pipe_mul2 <= _pipe_mul1;
-      _pipe_mul3 <= _pipe_mul2;
-      _pipe_mul4 <= _pipe_mul3;
     end 
   end
 

tests/extension/stream_/substream/test_stream_substream.py

@@ -191,7 +191,9 @@
 
   reg _mystream_stream_ivalid;
   wire _mystream_stream_oready;
-  assign _mystream_stream_oready = 1;
+  wire _mystream_stream_internal_oready;
+  assign _mystream_stream_internal_oready = 1;
+  assign _mystream_stream_oready = _mystream_stream_internal_oready;
   reg [32-1:0] _mystream_fsm;
   localparam _mystream_fsm_init = 0;
   wire _mystream_run_flag;
@@ -1103,13 +1105,13 @@
       _mystream_source_stop <= 0;
       _mystream_stream_ivalid <= 0;
     end else begin
-      if(_tmp_46 && _mystream_stream_oready) begin
+      if(_mystream_stream_oready && _tmp_46) begin
         _mystream_stream_ivalid <= 1;
       end 
       if(_mystream_stream_oready) begin
         _mystream_source_stop <= 0;
       end 
-      if(_tmp_49 && _mystream_stream_oready) begin
+      if(_mystream_stream_oready && _tmp_49) begin
         _mystream_stream_ivalid <= 0;
       end 
       case(_mystream_fsm)

tests/extension/thread_/stream_axi_stream/test_thread_stream_axi_stream.py

@@ -191,7 +191,9 @@
 
   reg _mystream_stream_ivalid;
   wire _mystream_stream_oready;
-  assign _mystream_stream_oready = 1;
+  wire _mystream_stream_internal_oready;
+  assign _mystream_stream_internal_oready = 1;
+  assign _mystream_stream_oready = _mystream_stream_internal_oready;
   reg [32-1:0] _mystream_fsm;
   localparam _mystream_fsm_init = 0;
   wire _mystream_run_flag;
@@ -1103,13 +1105,13 @@
       _mystream_source_stop <= 0;
       _mystream_stream_ivalid <= 0;
     end else begin
-      if(_tmp_46 && _mystream_stream_oready) begin
+      if(_mystream_stream_oready && _tmp_46) begin
         _mystream_stream_ivalid <= 1;
       end 
       if(_mystream_stream_oready) begin
         _mystream_source_stop <= 0;
       end 
-      if(_tmp_49 && _mystream_stream_oready) begin
+      if(_mystream_stream_oready && _tmp_49) begin
         _mystream_stream_ivalid <= 0;
       end 
       case(_mystream_fsm)