Merge branch 'fix_simulation_outputfile' into develop

Author: shtaxxx

.github/workflows/main.yml

@@ -19,7 +19,7 @@ jobs:
     runs-on: ubuntu-latest
     strategy:
       matrix:
-        python-version: [3.7, 3.8, 3.9]
+        python-version: ['3.9', '3.10', '3.11']
 
     # Steps represent a sequence of tasks that will be executed as part of the job
     steps:
@@ -37,8 +37,9 @@ jobs:
       - name: Install dependencies
         run: |
           python -m pip install --upgrade pip
-          pip install pytest pytest-pythonpath pyverilog numpy
+          pip install pytest pytest-pythonpath pytest-xdist pyverilog numpy
       # Run pytest
       - name: Test with pytest
         run: |
+          #python -m pytest -n auto tests examples
           python -m pytest tests examples

.travis.yml

@@ -3,9 +3,9 @@ language: python
 sudo: false
 
 python:
-  - 3.7
-  - 3.8
   - 3.9
+  - 3.10
+  - 3.11
 
 addons:
   apt:
@@ -14,7 +14,7 @@ addons:
     - verilator
 
 install:
-  - pip install pytest pytest-pythonpath pyverilog numpy
+  - pip install pytest pytest-pythonpath pytest-xdist pyverilog numpy
 
 script:
-  - python -m pytest tests examples
+  - python -m pytest -n auto tests examples

Makefile

@@ -15,7 +15,7 @@ clean:
 	make clean -C ./tests
 	make clean -C ./examples_obsolete
 	make clean -C ./tests_obsolete
-	rm -rf *.egg-info build dist *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd
+	rm -rf *.egg-info build dist *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v *.vcd
 
 #.PHONY: release
 #release:

examples/Makefile

@@ -14,5 +14,5 @@ run:
 
 .PHONY: clean
 clean:
-	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v *.vcd
 	find . -maxdepth 1 -type d | grep "./" | xargs -I {} make clean -C {}

examples/axi_stream_ultra96v2_pynq/Makefile

@@ -26,4 +26,4 @@ check:
 
 .PHONY: clean
 clean:
-	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v *.vcd

examples/chatter_clear/Makefile

@@ -26,4 +26,4 @@ check:
 
 .PHONY: clean
 clean:
-	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd 
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v *.vcd

examples/chatter_clear/chatter_clear.py

@@ -8,11 +8,12 @@
 
 from veriloggen import *
 
+
 def mkChatterClear(length=1024):
     m = Module("chatter_clear")
 
     length = m.Parameter('length', length)
-    
+
     clk = m.Input('CLK')
     rst = m.Input('RST')
 
@@ -22,28 +23,29 @@ def mkChatterClear(length=1024):
     seq = Seq(m, 'seq', clk, rst)
 
     count = m.TmpReg(32)
-    
-    seq.If(din==dout)(
+
+    seq.If(din == dout)(
         count(0)
     )
-    seq.If(din!=dout)(
+    seq.If(din != dout)(
         count.inc()
     )
-    
-    seq.If(count==length)(
+
+    seq.If(count == length)(
         count(0)
     )
-    seq.If(count==length)(
+    seq.If(count == length)(
         dout(din)
     )
 
     seq.make_always()
 
     return m
 
+
 def mkTest(length=1024):
     m = Module('test')
-    
+
     main = mkChatterClear(length)
     params = m.copy_params(main)
     ports = m.copy_sim_ports(main)
@@ -56,76 +58,78 @@ def mkTest(length=1024):
     fsm = FSM(m, 'fsm', clk, rst)
     count = m.TmpReg(32, initval=0)
 
-    fsm( din(0) )
-    fsm( count.inc() )
-    fsm.If(count==2000)( count(0) )
-    fsm.goto_next(count==2000)
-
-    fsm( din(1) )
-    fsm( count.inc() )
-    fsm.If(count==10)( count(0) )
-    fsm.goto_next(count==10)
-
-    fsm( din(0) )
-    fsm( count.inc() )
-    fsm.If(count==10)( count(0) )
-    fsm.goto_next(count==10)
-
-    fsm( din(1) )
-    fsm( count.inc() )
-    fsm.If(count==2000)( count(0) )
-    fsm.goto_next(count==2000)
-
-    fsm( din(0) )
-    fsm( count.inc() )
-    fsm.If(count==10)( count(0) )
-    fsm.goto_next(count==10)
-
-    fsm( din(1) )
-    fsm( count.inc() )
-    fsm.If(count==10)( count(0) )
-    fsm.goto_next(count==10)
-
-    fsm( din(0) )
-    fsm( count.inc() )
-    fsm.If(count==2000)( count(0) )
-    fsm.goto_next(count==2000)
+    fsm(din(0))
+    fsm(count.inc())
+    fsm.If(count == 2000)(count(0))
+    fsm.goto_next(count == 2000)
+
+    fsm(din(1))
+    fsm(count.inc())
+    fsm.If(count == 10)(count(0))
+    fsm.goto_next(count == 10)
+
+    fsm(din(0))
+    fsm(count.inc())
+    fsm.If(count == 10)(count(0))
+    fsm.goto_next(count == 10)
+
+    fsm(din(1))
+    fsm(count.inc())
+    fsm.If(count == 2000)(count(0))
+    fsm.goto_next(count == 2000)
+
+    fsm(din(0))
+    fsm(count.inc())
+    fsm.If(count == 10)(count(0))
+    fsm.goto_next(count == 10)
+
+    fsm(din(1))
+    fsm(count.inc())
+    fsm.If(count == 10)(count(0))
+    fsm.goto_next(count == 10)
+
+    fsm(din(0))
+    fsm(count.inc())
+    fsm.If(count == 2000)(count(0))
+    fsm.goto_next(count == 2000)
 
     fsm.make_always()
-    
+
     uut = m.Instance(main, 'uut',
                      params=m.connect_params(main),
                      ports=m.connect_ports(main))
 
-    simulation.setup_waveform(m, uut, m.get_vars())
+    vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd'
+    simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name)
     simulation.setup_clock(m, clk, hperiod=5)
     init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
 
     nclk = simulation.next_clock
-    
+
     init.add(
         Delay(1000 * 100),
         Systask('finish'),
     )
 
     return m
 
+
 if __name__ == '__main__':
     #main = mkChatterClear()
     #verilog = main.to_verilog('tmp.v')
-    #print(verilog)
-    #exit()
-    
+    # print(verilog)
+    # exit()
+
     test = mkTest()
     verilog = test.to_verilog('tmp.v')
     print(verilog)
 
     # run simulator (Icarus Verilog)
     sim = simulation.Simulator(test)
-    rslt = sim.run() # display=False
+    rslt = sim.run()  # display=False
     #rslt = sim.run(display=True)
     print(rslt)
 
     # launch waveform viewer (GTKwave)
-    #sim.view_waveform() # background=False
-    #sim.view_waveform(background=True)
+    # sim.view_waveform() # background=False
+    # sim.view_waveform(background=True)

examples/chatter_clear/test_chatter_clear.py

@@ -119,7 +119,7 @@
 
 
   initial begin
-    $dumpfile("uut.vcd");
+    $dumpfile("chatter_clear.vcd");
     $dumpvars(0, uut, CLK, RST, din, dout, fsm, _tmp_0);
   end
 

examples/counter/Makefile

@@ -26,4 +26,4 @@ check:
 
 .PHONY: clean
 clean:
-	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd 
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v *.vcd

examples/counter/counter.py

@@ -9,6 +9,7 @@
 
 from veriloggen import *
 
+
 def counter(m, clk, rst, width=None, maxval=None, cond=None, initval=0):
     if maxval is None and width is not None:
         maxval = Int(2) ** width
@@ -17,67 +18,71 @@ def counter(m, clk, rst, width=None, maxval=None, cond=None, initval=0):
     if maxval is None and width is None:
         width = 10
         maxval = 1024
-        
+
     c = m.TmpReg(width, initval=initval)
     seq = TmpSeq(m, clk, rst)
-    
+
     if cond is not None:
         # setting the following condition
         seq.If(cond)
-        
+
     seq(
-        If(c == maxval-1)(
+        If(c == maxval - 1)(
             c(0)
         ).Else(
             c.inc()
         )
     )
-    
+
     seq.make_always()
-    
+
     return c
 
+
 def mkLed(width=8):
     m = Module('blinkled')
     clk = m.Input('CLK')
     rst = m.Input('RST')
     led = m.Output('LED', width)
-    
+
     step = 1024
     count = counter(m, clk, rst, maxval=step)
-    led_count = counter(m, clk, rst, width=width, cond=(count==step-1))
+    led_count = counter(m, clk, rst, width=width, cond=(count == step - 1))
     led.assign(led_count)
-    
+
     return m
 
+
 def mkTest():
     m = Module('test')
-    
+
     # target instance
     led = mkLed()
-    
+
     # copy paras and ports
     params = m.copy_params(led)
     ports = m.copy_sim_ports(led)
-    
+
     clk = ports['CLK']
     rst = ports['RST']
-    
+
     uut = m.Instance(led, 'uut',
                      params=m.connect_params(led),
                      ports=m.connect_ports(led))
-    
-    simulation.setup_waveform(m, uut, m.get_vars())
+
+    vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd'
+    simulation.setup_waveform(m, uut, m.get_vars(), dumpfile=vcd_name)
     simulation.setup_clock(m, clk, hperiod=5)
     init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
-    
+
     init.add(
         Delay(1000 * 100),
         Systask('finish'),
     )
 
     return m
-    
+
+
 if __name__ == '__main__':
     test = mkTest()
     verilog = test.to_verilog(filename='tmp.v')
@@ -88,4 +93,4 @@ def mkTest():
     rslt = sim.run()
     print(rslt)
 
-    #sim.view_waveform()
+    # sim.view_waveform()