Explicit function definition is supported.

shtaxxx · shtaxxx · commit 865df5bdebab · 2015-07-10T17:53:48.000+09:00
diff --git a/sample/bram/bram.py b/sample/bram/bram.py
@@ -4,6 +4,9 @@
 
 from veriloggen import *
 
+#-------------------------------------------------------------------------------
+# BRAM interface
+#-------------------------------------------------------------------------------
 class BramInterface(Interface):
     def __init__(self, m, prefix='', postfix='', addrwidth=10, datawidth=32, direction='in'):
         Interface.__init__(self, m, prefix, postfix)
@@ -23,6 +26,9 @@ def __init__(self, m, prefix='', postfix='', addrwidth=10, datawidth=32, directi
         self.write = In('write')
         self.dataout = Out('dataout', datawidth)
     
+#-------------------------------------------------------------------------------
+# BRAM module
+#-------------------------------------------------------------------------------
 def mkBram(name):
     m = Module(name + 'bram')
     
@@ -44,12 +50,16 @@ def mkBram(name):
     
     return m
 
+#-------------------------------------------------------------------------------
+# Top module
+#-------------------------------------------------------------------------------
 def mkTop():
     m = Module('TOP')
     addrwidth = m.Parameter('ADDR_WIDTH', 10)
     datawidth = m.Parameter('DATA_WIDTH', 32)
     clk = m.Input('CLK')
     rst = m.Input('RST')
+
     bramif = BramInterface(m, prefix='bram_',
                            addrwidth=addrwidth, datawidth=datawidth, direction='out')
 
@@ -60,7 +70,7 @@ def mkTop():
     ports.update(clk.connect())
     ports.update(bramif.connect_all_ports())
 
-    m.Instance(bram, 'inst_bram', params, ports)
+    m.Instance(mkBram('my_'), 'inst_bram', params, ports)
 
     fsm = lib.FSM(m, 'fsm')
     m.Always(Posedge(clk))(
@@ -81,7 +91,7 @@ def mkTop():
     return m
 
 #-------------------------------------------------------------------------------
-bram = mkBram('my_')
 top = mkTop()
-verilog = ''.join( (bram.to_verilog(), top.to_verilog()) )
+# top.to_verilog('tmp.v')
+verilog = top.to_verilog()
 print(verilog)
diff --git a/sample/test/class/led.py b/sample/test/class/led.py
@@ -28,6 +28,58 @@ def __init__(self, name='blinkled'):
             ))
         
 #-------------------------------------------------------------------------------
-led = Led()
-verilog = led.to_verilog()
-print(verilog)
+import unittest
+
+expected_verilog = """
+module blinkled #
+  ( 
+   parameter WIDTH = 8
+  )
+  ( 
+   input CLK, 
+   input RST,
+   output reg [WIDTH-1:0] LED
+  );
+  reg [32-1:0] count;
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      count <= 0;
+    end else begin
+      count <= count + 1;
+    end
+  end
+  always @(posedge CLK) begin
+    if(RST) begin
+      LED <= 0;
+    end else begin
+      if(count == 1023) begin
+        LED <= LED + 1;
+      end 
+    end
+  end
+endmodule
+"""
+
+class TestLed(unittest.TestCase):
+    def setUp(self):
+        pass
+
+    def test_sample(self):
+        from pyverilog.vparser.parser import VerilogParser
+        from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+        led = Led()
+        verilog = led.to_verilog()
+        parser = VerilogParser()
+        expected_ast = parser.parse(expected_verilog)
+        codegen = ASTCodeGenerator()
+        expected_code = codegen.visit(expected_ast)
+        self.assertTrue( expected_code == verilog )
+        
+        #import difflib
+        #diff = difflib.unified_diff(verilog.splitlines(), expected_code.splitlines())
+        #print('\n'.join(list(diff)))
+        #self.assertTrue( len(list(diff)) == 0 )
+    
+if __name__ == '__main__':
+    unittest.main()
diff --git a/sample/test/function/Makefile b/sample/test/function/Makefile
@@ -0,0 +1,25 @@
+TARGET=led.py
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: run
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out
diff --git a/sample/test/function/led.py b/sample/test/function/led.py
@@ -0,0 +1,114 @@
+import sys
+import os
+
+from veriloggen import *
+
+def mkLed():
+    m = Module('blinkled')
+    width = m.Parameter('WIDTH', 8)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    led = m.OutputReg('LED', width)
+    count = m.Reg('count', 32)
+
+    inc = m.Function('inc', width)
+    inc_v = inc.Input('v', width)
+    inc_o = inc.Input('o', width)
+    inc_tmp = inc.Reg('tmp', width)
+    inc.Body(
+        inc_tmp(inc_v + 1),
+        inc(inc_tmp)
+    )
+    
+    m.Always(Posedge(clk))(
+        If(rst)(
+            count(0)
+        ).Else(
+            count( inc.call(count, 1) )
+        ))
+    
+    m.Always(Posedge(clk))(
+        If(rst)(
+            led(1)
+        ).Else(
+            If(count == 1024 - 1)(
+                led[0](led[width-1]),
+                led[width-1:1](led[width-2:0])
+            )
+        ))
+
+    return m
+
+#-------------------------------------------------------------------------------
+import unittest
+
+expected_verilog = """
+module blinkled #
+ (
+  parameter WIDTH = 8
+ )
+ (
+  input CLK, 
+  input RST, 
+  output reg [(WIDTH - 1):0] LED
+ );
+  reg [(32 - 1):0] count;
+
+  function [(WIDTH - 1):0] inc;
+    input [(WIDTH - 1):0] v;
+    input [(WIDTH - 1):0] o;
+    reg [(WIDTH - 1):0] tmp;
+    begin        
+      tmp = (v + 1);        
+      inc = tmp;
+    end 
+  endfunction
+
+  always @(posedge CLK)
+    begin        
+      if(RST) begin        
+        count <= 0;
+      end  
+      else begin        
+        count <= inc(count, 1);
+      end 
+    end 
+
+  always @(posedge CLK)
+    begin        
+      if(RST) begin        
+        LED <= 1;
+      end  
+      else begin        
+        if((count == 1023)) begin        
+          LED[0] <= LED[(WIDTH - 1)];        
+          LED[(WIDTH - 1):1] <= LED[(WIDTH - 2):0];
+        end  
+      end 
+    end 
+
+endmodule
+"""
+
+class TestLed(unittest.TestCase):
+    def setUp(self):
+        pass
+
+    def test_sample(self):
+        from pyverilog.vparser.parser import VerilogParser
+        from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+        led = mkLed()
+        verilog = led.to_verilog()
+        parser = VerilogParser()
+        expected_ast = parser.parse(expected_verilog)
+        codegen = ASTCodeGenerator()
+        expected_code = codegen.visit(expected_ast)
+        self.assertTrue( expected_code == verilog )
+        
+        #import difflib
+        #diff = difflib.unified_diff(verilog.splitlines(), expected_code.splitlines())
+        #print('\n'.join(list(diff)))
+        #self.assertTrue( len(list(diff)) == 0 )
+    
+if __name__ == '__main__':
+    unittest.main()
diff --git a/sample/test/function/veriloggen b/sample/test/function/veriloggen
@@ -0,0 +1 @@
+../../../veriloggen
diff --git a/veriloggen/__init__.py b/veriloggen/__init__.py
@@ -17,6 +17,7 @@
 
 from module import Module
 from interface import Interface
+from function import Function
 from vtypes import *
 
 import lib
diff --git a/veriloggen/function.py b/veriloggen/function.py
@@ -0,0 +1,51 @@
+import os
+import sys
+import collections
+
+sys.path.insert(0, os.path.dirname(os.path.abspath(__file__)))
+
+import vtypes
+
+class Function(vtypes.VeriloggenNode):
+    def __init__(self, name, width=1):
+        self.name = name
+        self.width = width
+        self.io_variable = collections.OrderedDict()
+        self.variable = collections.OrderedDict()
+        self.statement = None
+
+    #---------------------------------------------------------------------------
+    def Input(self, name, width=None, length=None, signed=False, value=None):
+        t = vtypes.Input(name, width, length, signed, value)
+        self.io_variable[name] = t
+        return t
+    
+    def Reg(self, name, width=None, length=None, signed=False, value=None):
+        t = vtypes.Reg(name, width, length, signed, value)
+        self.variable[name] = t
+        return t
+    
+    def Integer(self, name, width=None, length=None, signed=False, value=None):
+        t = vtypes.Integer(name, width, length, signed, value)
+        self.variable[name] = t
+        return t
+    
+    def Body(self, *statement):
+        if self.statement is not None:
+            raise ValueError("Statement is already assigned.")
+        self.statement = tuple(statement)
+        return self
+
+    def __call__(self, r):
+        return vtypes.Subst(self, r)
+
+    def next(self, r):
+        return self.__call__(r)
+    
+    def call(self, *args):
+        return FunctionCall(self.name, *args)
+
+class FunctionCall(vtypes.VeriloggenNode):
+    def __init__(self, name, *args):
+        self.name = name
+        self.args = tuple(args)
diff --git a/veriloggen/interface.py b/veriloggen/interface.py
@@ -6,10 +6,13 @@
 sys.path.insert(0, os.path.dirname(os.path.abspath(__file__)))
 
 import vtypes
+import module
 
 class Interface(vtypes.VeriloggenNode):
-    def __init__(self, module, prefix='', postfix=''):
-        self.module = module
+    def __init__(self, m, prefix='', postfix=''):
+        if not isinstance(m, module.Module):
+            raise TypeError("module should be an instance of module.Module.")
+        self.module = m
         self.prefix = prefix
         self.postfix = postfix
 
diff --git a/veriloggen/module.py b/veriloggen/module.py
@@ -5,6 +5,8 @@
 sys.path.insert(0, os.path.dirname(os.path.abspath(__file__)))
 
 import vtypes
+import function
+
 import to_verilog
 
 class Module(object):
@@ -15,9 +17,11 @@ def __init__(self, name=None):
         self.io_variable = collections.OrderedDict()
         self.constant = collections.OrderedDict()
         self.global_constant = collections.OrderedDict()
+        self.function = []
         self.assign = []
         self.always = []
         self.instance = collections.OrderedDict()
+        self.submodule = {}
 
     #---------------------------------------------------------------------------
     def Input(self, name, width=None, length=None, signed=False, value=None):
@@ -52,6 +56,21 @@ def Reg(self, name, width=None, length=None, signed=False, value=None):
         self.variable[name] = t
         return t
     
+    def Integer(self, name, width=None, length=None, signed=False, value=None):
+        t = vtypes.Integer(name, width, length, signed, value)
+        self.variable[name] = t
+        return t
+    
+    def Real(self, name, width=None, length=None, signed=False, value=None):
+        t = vtypes.Real(name, width, length, signed, value)
+        self.variable[name] = t
+        return t
+    
+    def Genvar(self, name, width=None, length=None, signed=False, value=None):
+        t = vtypes.Genvar(name, width, length, signed, value)
+        self.variable[name] = t
+        return t
+    
     def Parameter(self, name, value, width=None, signed=False, length=None):
         t = vtypes.Parameter(name, value, width, signed)
         self.global_constant[name] = t
@@ -73,9 +92,17 @@ def Assign(self, statement):
         self.assign.append(t)
         return t
 
+    #---------------------------------------------------------------------------
+    def Function(self, name, width=1):
+        t = function.Function(name, width)
+        self.function.append(t)
+        return t
+        
+    #---------------------------------------------------------------------------
     def Instance(self, module, instname, params, ports):
         t = vtypes.Instance(module, instname, params, ports)
         self.instance[instname] = t
+        self.submodule[module.name] = module
         return t
     
     #---------------------------------------------------------------------------
diff --git a/veriloggen/to_verilog.py b/veriloggen/to_verilog.py
diff --git a/veriloggen/vtypes.py b/veriloggen/vtypes.py
