The number of skid buffer stages can be modified.

shtaxxx · shtaxxx · commit 8634475b9519 · 2023-05-10T11:14:13.000+09:00
diff --git a/tests/extension/thread_/axi_dma_sb_depth/Makefile b/tests/extension/thread_/axi_dma_sb_depth/Makefile
@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v *.vcd
diff --git a/tests/extension/thread_/axi_dma_sb_depth/test_thread_axi_dma_sb_depth.py b/tests/extension/thread_/axi_dma_sb_depth/test_thread_axi_dma_sb_depth.py
@@ -0,0 +1,18 @@
+from __future__ import absolute_import
+from __future__ import print_function
+
+import os
+import veriloggen
+import thread_axi_dma_sb_depth
+
+
+def test(request):
+    veriloggen.reset()
+
+    simtype = request.config.getoption('--sim')
+
+    rslt = thread_axi_dma_sb_depth.run(filename=None, simtype=simtype,
+                                       outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
+
+    verify_rslt = rslt.splitlines()[-1]
+    assert(verify_rslt == '# verify: PASSED')
diff --git a/tests/extension/thread_/axi_dma_sb_depth/thread_axi_dma_sb_depth.py b/tests/extension/thread_/axi_dma_sb_depth/thread_axi_dma_sb_depth.py
@@ -0,0 +1,157 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+import veriloggen.thread as vthread
+import veriloggen.types.axi as axi
+
+
+def mkLed():
+    m = Module('blinkled')
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+
+    datawidth = 32
+    addrwidth = 10
+    myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth,
+                         sb_depth=3)
+    myram0 = vthread.RAM(m, 'myram0', clk, rst, datawidth, addrwidth)
+    myram1 = vthread.RAM(m, 'myram1', clk, rst, datawidth, addrwidth)
+
+    all_ok = m.TmpReg(initval=0, prefix='all_ok')
+    wdata = m.TmpReg(width=datawidth, initval=0, prefix='wdata')
+    rdata = m.TmpReg(width=datawidth, initval=0, prefix='rdata')
+    rexpected = m.TmpReg(width=datawidth, initval=0, prefix='rexpected')
+
+    def blink(size):
+        all_ok.value = True
+
+        for i in range(4):
+            print('# iter %d start' % i)
+            # Test for 4KB boundary check
+            offset = i * 1024 * 16 + (myaxi.boundary_size - (datawidth // 8) * 3)
+            body(size, offset)
+            print('# iter %d end' % i)
+
+        if all_ok:
+            print('# verify: PASSED')
+        else:
+            print('# verify: FAILED')
+
+        vthread.finish()
+
+    def body(size, offset):
+        # write
+        for i in range(size):
+            wdata.value = i + 0x1000
+            myram0.write(i, wdata)
+
+        laddr = 0
+        gaddr = offset
+        myaxi.dma_write(myram0, laddr, gaddr, size)
+        print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
+
+        # write
+        for i in range(size):
+            wdata.value = i + 0x4000
+            myram1.write(i, wdata)
+
+        laddr = 0
+        gaddr = (size + size) * 4 + offset
+        myaxi.dma_write(myram1, laddr, gaddr, size)
+        print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
+
+        # read
+        laddr = 0
+        gaddr = offset
+        myaxi.dma_read(myram1, laddr, gaddr, size)
+        print('dma_read:  [%d] <- [%d]' % (laddr, gaddr))
+
+        for i in range(size):
+            rdata.value = myram1.read(i)
+            rexpected.value = i + 0x1000
+            if vthread.verilog.NotEql(rdata, rexpected):
+                print('rdata[%d] = %d (expected %d)' % (i, rdata, rexpected))
+                all_ok.value = False
+
+        # read
+        laddr = 0
+        gaddr = (size + size) * 4 + offset
+        myaxi.dma_read(myram0, laddr, gaddr, size)
+        print('dma_read:  [%d] <- [%d]' % (laddr, gaddr))
+
+        for i in range(size):
+            rdata.value = myram0.read(i)
+            rexpected.value = i + 0x4000
+            if vthread.verilog.NotEql(rdata, rexpected):
+                print('rdata[%d] = %d (expected %d)' % (i, rdata, rexpected))
+                all_ok.value = False
+
+    th = vthread.Thread(m, 'th_blink', clk, rst, blink)
+    fsm = th.start(16)
+
+    return m
+
+
+def mkTest(memimg_name=None):
+    m = Module('test')
+
+    # target instance
+    led = mkLed()
+
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+
+    clk = ports['CLK']
+    rst = ports['RST']
+
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name)
+    memory.connect(ports, 'myaxi')
+
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+
+    # vcd_name = os.path.splitext(os.path.basename(__file__))[0] + '.vcd'
+    # simulation.setup_waveform(m, uut, dumpfile=vcd_name)
+    simulation.setup_clock(m, clk, hperiod=5)
+    init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
+
+    init.add(
+        Delay(1000000),
+        Systask('finish'),
+    )
+
+    return m
+
+
+def run(filename='tmp.v', simtype='iverilog', outputfile=None):
+
+    if outputfile is None:
+        outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
+
+    memimg_name = 'memimg_' + outputfile
+
+    test = mkTest(memimg_name=memimg_name)
+
+    if filename is not None:
+        test.to_verilog(filename)
+
+    sim = simulation.Simulator(test, sim=simtype)
+    rslt = sim.run(outputfile=outputfile)
+    lines = rslt.splitlines()
+    if simtype == 'verilator' and lines[-1].startswith('-'):
+        rslt = '\n'.join(lines[:-1])
+    return rslt
+
+
+if __name__ == '__main__':
+    rslt = run(filename='tmp.v')
+    print(rslt)
diff --git a/veriloggen/thread/axim.py b/veriloggen/thread/axim.py
@@ -43,10 +43,12 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
                  waddr_prot_mode=axi.AxPROT_NONCOHERENT, raddr_prot_mode=axi.AxPROT_NONCOHERENT,
                  waddr_user_mode=axi.AxUSER_NONCOHERENT, wdata_user_mode=axi.xUSER_DEFAULT,
                  raddr_user_mode=axi.AxUSER_NONCOHERENT,
-                 noio=False,
+                 noio=False, sb_depth=1,
                  use_global_base_addr=False,
-                 op_sel_width=8, req_fifo_addrwidth=3, fsm_as_module=False):
+                 op_sel_width=8, req_fifo_addrwidth=3,
+                 fsm_as_module=False):
 
+        outstanding_wcount_width = req_fifo_addrwidth
         axi.AxiMaster.__init__(self, m, name, clk, rst, datawidth, addrwidth,
                                waddr_id_width, wdata_id_width, wresp_id_width,
                                raddr_id_width, rdata_id_width,
@@ -57,7 +59,7 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
                                waddr_prot_mode, raddr_prot_mode,
                                waddr_user_mode, wdata_user_mode,
                                raddr_user_mode,
-                               noio, req_fifo_addrwidth)
+                               noio, outstanding_wcount_width, sb_depth)
 
         self.use_global_base_addr = use_global_base_addr
         self.op_sel_width = op_sel_width
@@ -1807,14 +1809,15 @@ class AXIMLite(axi.AxiLiteMaster, _MutexFunction):
     def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
                  waddr_cache_mode=axi.AxCACHE_NONCOHERENT, raddr_cache_mode=axi.AxCACHE_NONCOHERENT,
                  waddr_prot_mode=axi.AxPROT_NONCOHERENT, raddr_prot_mode=axi.AxPROT_NONCOHERENT,
-                 noio=False,
+                 noio=False, sb_depth=1,
                  use_global_base_addr=False,
                  fsm_as_module=False):
 
+        outstanding_wcount_width = 3
         axi.AxiLiteMaster.__init__(self, m, name, clk, rst, datawidth, addrwidth,
                                    waddr_cache_mode, raddr_cache_mode,
                                    waddr_prot_mode, raddr_prot_mode,
-                                   noio)
+                                   noio, outstanding_wcount_width, sb_depth)
 
         self.use_global_base_addr = use_global_base_addr
         self.fsm_as_module = fsm_as_module
diff --git a/veriloggen/types/axi.py b/veriloggen/types/axi.py
