lib.pipeline -> lib.dataflow

shtaxxx · shtaxxx · commit 826bebe6879a · 2015-11-15T22:49:06.000+09:00
diff --git a/tests/lib_dataflow_/Makefile b/tests/lib_dataflow_/Makefile
diff --git a/tests/lib_dataflow_/acc_add/Makefile b/tests/lib_dataflow_/acc_add/Makefile
diff --git a/tests/lib_dataflow_/acc_add/lib_dataflow_acc_add.py b/tests/lib_dataflow_/acc_add/lib_dataflow_acc_add.py
@@ -14,7 +14,7 @@ def mkLed():
     y = m.Output('y', 32)
     prst = m.Input('prst')
     
-    pipe = lib.Pipeline(m, 'pipe', clk, rst)
+    pipe = lib.Dataflow(m, 'pipe', clk, rst)
     
     px = pipe.input(x)
     psum = pipe.acc_add(px, initval=0, resetcond=prst)
diff --git a/tests/lib_dataflow_/acc_add/test_lib_dataflow_acc_add.py b/tests/lib_dataflow_/acc_add/test_lib_dataflow_acc_add.py
@@ -1,4 +1,4 @@
-import lib_pipeline_acc_add
+import lib_dataflow_acc_add
 
 expected_verilog = """
 module test;
@@ -143,7 +143,7 @@
 """
 
 def test():
-    test_module = lib_pipeline_acc_add.mkTest()
+    test_module = lib_dataflow_acc_add.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/lib_dataflow_/acc_add_valid/Makefile b/tests/lib_dataflow_/acc_add_valid/Makefile
diff --git a/tests/lib_dataflow_/acc_add_valid/lib_dataflow_acc_add_valid.py b/tests/lib_dataflow_/acc_add_valid/lib_dataflow_acc_add_valid.py
@@ -16,7 +16,7 @@ def mkLed():
     vy = m.Output('vy')
     prst = m.Input('prst')
     
-    pipe = lib.Pipeline(m, 'pipe', clk, rst)
+    pipe = lib.Dataflow(m, 'pipe', clk, rst)
 
     px = pipe.input(x, valid=vx)
     psum = pipe.acc_add(px, initval=0, resetcond=prst)
diff --git a/tests/lib_dataflow_/acc_add_valid/test_lib_dataflow_acc_add_valid.py b/tests/lib_dataflow_/acc_add_valid/test_lib_dataflow_acc_add_valid.py
@@ -1,4 +1,4 @@
-import lib_pipeline_acc_add_valid
+import lib_dataflow_acc_add_valid
 
 expected_verilog = """
 module test;
@@ -146,7 +146,7 @@
 """
 
 def test():
-    test_module = lib_pipeline_acc_add_valid.mkTest()
+    test_module = lib_dataflow_acc_add_valid.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/lib_dataflow_/acc_add_validready/Makefile b/tests/lib_dataflow_/acc_add_validready/Makefile
diff --git a/tests/lib_dataflow_/acc_add_validready/lib_dataflow_acc_add_validready.py b/tests/lib_dataflow_/acc_add_validready/lib_dataflow_acc_add_validready.py
@@ -18,7 +18,7 @@ def mkLed():
     ry = m.Input('ry')
     prst = m.Input('prst')
     
-    pipe = lib.Pipeline(m, 'pipe', clk, rst)
+    pipe = lib.Dataflow(m, 'pipe', clk, rst)
 
     px = pipe.input(x, valid=vx, ready=rx)
     psum = pipe.acc_add(px, initval=0, resetcond=prst)
diff --git a/tests/lib_dataflow_/acc_add_validready/test_lib_dataflow_acc_add_validready.py b/tests/lib_dataflow_/acc_add_validready/test_lib_dataflow_acc_add_validready.py
@@ -1,4 +1,4 @@
-import lib_pipeline_acc_add_validready
+import lib_dataflow_acc_add_validready
 
 expected_verilog = """
 module test;
@@ -256,7 +256,7 @@
 """
 
 def test():
-    test_module = lib_pipeline_acc_add_validready.mkTest()
+    test_module = lib_dataflow_acc_add_validready.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/lib_dataflow_/multi_input/Makefile b/tests/lib_dataflow_/multi_input/Makefile
diff --git a/tests/lib_dataflow_/multi_input/lib_dataflow_multi_input.py b/tests/lib_dataflow_/multi_input/lib_dataflow_multi_input.py
@@ -23,7 +23,7 @@ def mkLed():
     vz = m.Output('vz')
     rz = m.Input('rz')
     
-    pipe = lib.Pipeline(m, 'pipe', clk, rst)
+    pipe = lib.Dataflow(m, 'pipe', clk, rst)
     
     px = pipe.input(x, valid=vx, ready=rx)
     py = pipe.input(y, valid=vy, ready=ry)
diff --git a/tests/lib_dataflow_/multi_input/test_lib_dataflow_multi_input.py b/tests/lib_dataflow_/multi_input/test_lib_dataflow_multi_input.py
@@ -1,4 +1,4 @@
-import lib_pipeline_multi_input
+import lib_dataflow_multi_input
 
 expected_verilog = """
 module test;
@@ -297,7 +297,7 @@
 """
 
 def test():
-    test_module = lib_pipeline_multi_input.mkTest()
+    test_module = lib_dataflow_multi_input.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/lib_dataflow_/multi_output/Makefile b/tests/lib_dataflow_/multi_output/Makefile
diff --git a/tests/lib_dataflow_/multi_output/lib_dataflow_multi_output.py b/tests/lib_dataflow_/multi_output/lib_dataflow_multi_output.py
@@ -27,7 +27,7 @@ def mkLed():
     va = m.Output('va')
     ra = m.Input('ra')
     
-    pipe = lib.Pipeline(m, 'pipe', clk, rst)
+    pipe = lib.Dataflow(m, 'pipe', clk, rst)
     
     px = pipe.input(x, valid=vx, ready=rx)
     py = pipe.input(y, valid=vy, ready=ry)
diff --git a/tests/lib_dataflow_/multi_output/test_lib_dataflow_multi_output.py b/tests/lib_dataflow_/multi_output/test_lib_dataflow_multi_output.py
@@ -1,4 +1,4 @@
-import lib_pipeline_multi_output
+import lib_dataflow_multi_output
 
 expected_verilog = """
 module test;
@@ -471,7 +471,7 @@
 """
 
 def test():
-    test_module = lib_pipeline_multi_output.mkTest()
+    test_module = lib_dataflow_multi_output.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/lib_dataflow_/select/Makefile b/tests/lib_dataflow_/select/Makefile
diff --git a/tests/lib_dataflow_/select/lib_dataflow_select.py b/tests/lib_dataflow_/select/lib_dataflow_select.py
@@ -23,7 +23,7 @@ def mkLed():
     vz = m.Output('vz')
     rz = m.Input('rz')
     
-    pipe = lib.Pipeline(m, 'pipe', clk, rst)
+    pipe = lib.Dataflow(m, 'pipe', clk, rst)
     
     px = pipe.input(x, valid=vx, ready=rx)
     py = pipe.input(y, valid=vy, ready=ry)
diff --git a/tests/lib_dataflow_/select/test_lib_dataflow_select.py b/tests/lib_dataflow_/select/test_lib_dataflow_select.py
@@ -1,4 +1,4 @@
-import lib_pipeline_select
+import lib_dataflow_select
 
 expected_verilog = """
 module test;
@@ -297,7 +297,7 @@
 """
 
 def test():
-    test_module = lib_pipeline_select.mkTest()
+    test_module = lib_dataflow_select.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/lib_dataflow_/single_add/Makefile b/tests/lib_dataflow_/single_add/Makefile
diff --git a/tests/lib_dataflow_/single_add/lib_dataflow_single_add.py b/tests/lib_dataflow_/single_add/lib_dataflow_single_add.py
@@ -13,7 +13,7 @@ def mkLed():
     x = m.Input('x', 32)
     y = m.Output('y', 32)
     
-    pipe = lib.Pipeline(m, 'pipe', clk, rst)
+    pipe = lib.Dataflow(m, 'pipe', clk, rst)
     
     px = pipe.input(x)
     t0 = pipe(px.prev(1) + px.prev(2))
diff --git a/tests/lib_dataflow_/single_add/test_lib_dataflow_single_add.py b/tests/lib_dataflow_/single_add/test_lib_dataflow_single_add.py
@@ -1,4 +1,4 @@
-import lib_pipeline_single_add
+import lib_dataflow_single_add
 
 expected_verilog = """
 module test;
@@ -145,7 +145,7 @@
 """
 
 def test():
-    test_module = lib_pipeline_single_add.mkTest()
+    test_module = lib_dataflow_single_add.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/lib_dataflow_/single_add_valid/Makefile b/tests/lib_dataflow_/single_add_valid/Makefile
diff --git a/tests/lib_dataflow_/single_add_valid/lib_dataflow_single_add_valid.py b/tests/lib_dataflow_/single_add_valid/lib_dataflow_single_add_valid.py
@@ -15,7 +15,7 @@ def mkLed():
     y = m.Output('y', 32)
     vy = m.Output('vy')
     
-    pipe = lib.Pipeline(m, 'pipe', clk, rst)
+    pipe = lib.Dataflow(m, 'pipe', clk, rst)
     
     px = pipe.input(x, valid=vx)
     t0 = pipe(px.prev(2) + px.prev(3))
diff --git a/tests/lib_dataflow_/single_add_valid/test_lib_dataflow_single_add_valid.py b/tests/lib_dataflow_/single_add_valid/test_lib_dataflow_single_add_valid.py
@@ -1,4 +1,4 @@
-import lib_pipeline_single_add_valid
+import lib_dataflow_single_add_valid
 
 expected_verilog = """
 module test;
@@ -189,7 +189,7 @@
 """
 
 def test():
-    test_module = lib_pipeline_single_add_valid.mkTest()
+    test_module = lib_dataflow_single_add_valid.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/lib_dataflow_/single_add_validready/Makefile b/tests/lib_dataflow_/single_add_validready/Makefile
diff --git a/tests/lib_dataflow_/single_add_validready/lib_dataflow_single_add_validready.py b/tests/lib_dataflow_/single_add_validready/lib_dataflow_single_add_validready.py
@@ -17,7 +17,7 @@ def mkLed():
     vy = m.Output('vy')
     ry = m.Input('ry')
     
-    pipe = lib.Pipeline(m, 'pipe', clk, rst)
+    pipe = lib.Dataflow(m, 'pipe', clk, rst)
     
     px = pipe.input(x, valid=vx, ready=rx)
     t0 = pipe(px.prev(1) + px.prev(2))
diff --git a/tests/lib_dataflow_/single_add_validready/test_lib_dataflow_single_add_validready.py b/tests/lib_dataflow_/single_add_validready/test_lib_dataflow_single_add_validready.py
@@ -1,4 +1,4 @@
-import lib_pipeline_single_add_validready
+import lib_dataflow_single_add_validready
 
 expected_verilog = """
 module test;
@@ -294,7 +294,7 @@
 """
 
 def test():
-    test_module = lib_pipeline_single_add_validready.mkTest()
+    test_module = lib_dataflow_single_add_validready.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/lib_dataflow_/single_passthrough/Makefile b/tests/lib_dataflow_/single_passthrough/Makefile
diff --git a/tests/lib_dataflow_/single_passthrough/lib_dataflow_single_passthrough.py b/tests/lib_dataflow_/single_passthrough/lib_dataflow_single_passthrough.py
@@ -17,7 +17,7 @@ def mkLed():
     vy = m.Output('vy')
     ry = m.Input('ry')
     
-    pipe = lib.Pipeline(m, 'pipe', clk, rst)
+    pipe = lib.Dataflow(m, 'pipe', clk, rst)
     
     px = pipe.input(x, valid=vx, ready=rx)
     dummy = pipe(px)
diff --git a/tests/lib_dataflow_/single_passthrough/test_lib_dataflow_single_passthrough.py b/tests/lib_dataflow_/single_passthrough/test_lib_dataflow_single_passthrough.py
@@ -1,4 +1,4 @@
-import lib_pipeline_single_passthrough
+import lib_dataflow_single_passthrough
 
 expected_verilog = """
 module test;
@@ -242,7 +242,7 @@
 """
 
 def test():
-    test_module = lib_pipeline_single_passthrough.mkTest()
+    test_module = lib_dataflow_single_passthrough.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/tests/lib_dataflow_/unbalanced_output/Makefile b/tests/lib_dataflow_/unbalanced_output/Makefile
diff --git a/tests/lib_dataflow_/unbalanced_output/lib_dataflow_unbalanced_output.py b/tests/lib_dataflow_/unbalanced_output/lib_dataflow_unbalanced_output.py
@@ -23,7 +23,7 @@ def mkLed():
     vz = m.Output('vz')
     rz = m.Input('rz')
     
-    pipe = lib.Pipeline(m, 'pipe', clk, rst)
+    pipe = lib.Dataflow(m, 'pipe', clk, rst)
     
     px = pipe.input(x, valid=vx, ready=rx)
     py = pipe(px + 1)
diff --git a/tests/lib_dataflow_/unbalanced_output/test_lib_dataflow_unbalanced_output.py b/tests/lib_dataflow_/unbalanced_output/test_lib_dataflow_unbalanced_output.py
@@ -1,4 +1,4 @@
-import lib_pipeline_unbalanced_output
+import lib_dataflow_unbalanced_output
 
 expected_verilog = """
 module test;
@@ -398,7 +398,7 @@
 """
 
 def test():
-    test_module = lib_pipeline_unbalanced_output.mkTest()
+    test_module = lib_dataflow_unbalanced_output.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
diff --git a/veriloggen/lib/__init__.py b/veriloggen/lib/__init__.py
@@ -14,6 +14,6 @@
 ## Please add import notations here for additional library
 from .fsm import FSM
 from .seq import Seq
-from .pipeline import Pipeline
+from .dataflow import Dataflow
 from .bundle import Bundle
 from . import simulation
diff --git a/veriloggen/lib/dataflow.py b/veriloggen/lib/dataflow.py
@@ -7,8 +7,8 @@
 import veriloggen.vtypes as vtypes
 from veriloggen.lib.seq import Seq
 
-class Pipeline(vtypes.VeriloggenNode):
-    """ Pipeline Generator """
+class Dataflow(vtypes.VeriloggenNode):
+    """ Dataflow Generator """
     def __init__(self, m, name, clk, rst, width=32):
         self.m = m
         self.name = name
@@ -23,9 +23,9 @@ def __init__(self, m, name, clk, rst, width=32):
     #---------------------------------------------------------------------------
     def input(self, data, valid=None, ready=None, width=None):
         if ready is not None and not isinstance(ready, (vtypes.Wire, vtypes.Output)):
-            raise TypeError('ready port of PipelineVariable must be Wire., not %s' %
+            raise TypeError('ready port of DataflowVariable must be Wire., not %s' %
                             str(type(ready)))
-        ret = _PipelineVariable(self, 0, data, valid, ready)
+        ret = _DataflowVariable(self, 0, data, valid, ready)
         self.vars.append(ret)
         return ret
         
@@ -37,7 +37,7 @@ def stage(self, data, initval=0, width=None):
         tmp_data, tmp_valid, tmp_ready = self._make_tmp(raw_data, raw_valid, raw_ready,
                                                        width, initval)
         next_stage_id = stage_id + 1 if stage_id is not None else None
-        ret = _PipelineVariable(self, next_stage_id, tmp_data, tmp_valid, tmp_ready)
+        ret = _DataflowVariable(self, next_stage_id, tmp_data, tmp_valid, tmp_ready)
         self.vars.append(ret)
         return ret
 
@@ -102,7 +102,7 @@ def _accumulate(self, ops, data, width=None, initval=0, resetcond=None):
         tmp_data, tmp_valid, tmp_ready = self._make_tmp(raw_data, raw_valid, raw_ready,
                                                        width, initval, acc_ops=ops)
         next_stage_id = stage_id + 1 if stage_id is not None else None
-        ret = _PipelineVariable(self, next_stage_id, tmp_data, tmp_valid, tmp_ready)
+        ret = _DataflowVariable(self, next_stage_id, tmp_data, tmp_valid, tmp_ready)
         if resetcond is not None:
             ret.reset(resetcond, initval)
         self.vars.append(ret)
@@ -285,9 +285,9 @@ def __call__(self, data, initval=0, width=None):
         return self.stage(data, initval=initval, width=width)
     
 #-------------------------------------------------------------------------------
-class _PipelineNumeric(vtypes._Numeric): pass
+class _DataflowNumeric(vtypes._Numeric): pass
 
-class _PipelineVariable(_PipelineNumeric):
+class _DataflowVariable(_DataflowNumeric):
     def __init__(self, pipe, stage_id, data, valid=None, ready=None):
         self.pipe = pipe
         self.stage_id = stage_id
@@ -318,7 +318,7 @@ def prev(self, index, initval=0):
             
             tmp_data, tmp_valid, tmp_ready = self.pipe._make_prev(p.data, p.valid, p.ready,
                                                                  self.valid, width, initval)
-            p = _PipelineVariable(self.pipe, p.stage_id, tmp_data, tmp_valid, tmp_ready)
+            p = _DataflowVariable(self.pipe, p.stage_id, tmp_data, tmp_valid, tmp_ready)
             self.pipe.vars.append(p)
             self.prev_dict[i+1] = p
             
@@ -365,7 +365,7 @@ def bit_length(self):
         return self.data.bit_length()
             
 #-------------------------------------------------------------------------------
-class _PipelineVisitor(object):
+class _DataflowVisitor(object):
     def generic_visit(self, node):
         raise TypeError("Type %s is not supported." % str(type(node)))
     
@@ -385,8 +385,8 @@ def visit(self, node):
         visitor = getattr(self, 'visit_' + node.__class__.__name__, self.generic_visit)
         return visitor(node)
     
-    def visit__PipelineVariable(self, node):
-        raise NotImplementedError('visit__PipelineVariable() must be implemented')
+    def visit__DataflowVariable(self, node):
+        raise NotImplementedError('visit__DataflowVariable() must be implemented')
         
     def visit__BinaryOperator(self, node):
         raise NotImplementedError('visit__BinaryOperator() must be implemented')
@@ -428,7 +428,7 @@ def visit_float(self, node):
         raise NotImplementedError('visit__Constant() must be implemented')
     
 #-------------------------------------------------------------------------------
-class DataVisitor(_PipelineVisitor):
+class DataVisitor(_DataflowVisitor):
     def __init__(self, pipe):
         self.pipe = pipe
 
@@ -498,7 +498,7 @@ def make_valid(self, valid, ready):
             next_valid = None
         return next_valid
     
-    def visit__PipelineVariable(self, node):
+    def visit__DataflowVariable(self, node):
         ready = [] if node.ready is None else [ node.ready ]
         valid = self.make_valid(node.valid, node.ready)
         return (node.stage_id, node.data, valid, ready )
