Merge branch 'feature_axi_memory_model_addrwidth' into develop

Author: shtaxxx

.travis.yml

@@ -3,7 +3,7 @@ language: python
 sudo: false
 
 python:
-  - 3.6
+  - 3.7
 
 addons:
   apt:
@@ -12,7 +12,7 @@ addons:
     - verilator
 
 install:
-  - pip install jinja2 pytest pytest-pythonpath pyverilog ipgen numpy
+  - pip install pytest pytest-pythonpath jinja2 pyverilog numpy
 
 script:
   - python -m pytest tests examples

README.md

@@ -83,8 +83,8 @@ Requirements
 sudo apt install iverilog
 ```
 
-- Pyverilog: 1.1.4 or later
 - Jinja2: 2.10 or later
+- Pyverilog: 1.1.4 or later
 - NumPy: 1.14 or later
 
 ```
@@ -104,6 +104,14 @@ We recommend to install these testing library to verify experimental features.
 pip3 install pytest pytest-pythonpath
 ```
 
+For fast RTL simulation, we recommend to install Verilator.
+
+- Verilator: 3.916 or later
+
+```
+sudo apt install verilator
+```
+
 Optional installation for visualization
 --------------------
 
@@ -140,6 +148,26 @@ make
 ```
 
 
+Examples and testing
+==============================
+
+There are some exapmles in **examples** and various testing codes in **tests**.
+The testing codes are actually good small examples suggesting how to represent a desired function.
+
+To run the testing codes, please type the following commands.
+
+```
+cd tests
+python3 -m pytest .
+```
+
+If you use Verilator instead of Icarus Verilog for RTL simulation, set "--sim" option.
+
+```
+python3 -m pytest --sim=verilator .
+```
+
+
 Getting started
 ==============================
 

README.rst

@@ -96,8 +96,8 @@ Requirements
 
    sudo apt install iverilog
 
--  Pyverilog: 1.1.4 or later
 -  Jinja2: 2.10 or later
+-  Pyverilog: 1.1.4 or later
 -  NumPy: 1.14 or later
 
 ::
@@ -118,6 +118,14 @@ features.
 
    pip3 install pytest pytest-pythonpath
 
+For fast RTL simulation, we recommend to install Verilator.
+
+-  Verilator: 3.916 or later
+
+::
+
+   sudo apt install verilator
+
 Optional installation for visualization
 ---------------------------------------
 
@@ -155,6 +163,27 @@ without any installation on your host platform.
    cd veriloggen/examples/led/
    make
 
+Examples and testing
+====================
+
+There are some exapmles in **examples** and various testing codes in
+**tests**. The testing codes are actually good small examples suggesting
+how to represent a desired function.
+
+To run the testing codes, please type the following commands.
+
+::
+
+   cd tests
+   python3 -m pytest .
+
+If you use Verilator instead of Icarus Verilog for RTL simulation, set
+“–sim” option.
+
+::
+
+   python3 -m pytest --sim=verilator .
+
 Getting started
 ===============
 

docker/Dockerfile

@@ -3,8 +3,9 @@ RUN apt update && apt upgrade -y
 RUN apt install build-essential -y
 RUN apt install git -y
 RUN apt install python3 python3-pip -y
-RUN apt install iverilog gtkwave -y
-RUN pip3 install jinja2 numpy pytest pytest-pythonpath pyverilog
+RUN apt install iverilog verilator gtkwave -y
+RUN pip3 install jinja2 pyverilog numpy
+RUN pip3 install pytest pytest-pythonpath
 RUN mkdir /home/veriloggen/
 WORKDIR "/home/veriloggen"
 RUN git clone https://github.com/PyHDI/veriloggen.git

setup.py

@@ -23,8 +23,8 @@ def read(filename):
       packages=find_packages(),
       package_data={'veriloggen.utils': ['VERSION'],
                     'veriloggen.simulation': ['*.cpp'], },
-      install_requires=['pyverilog>=1.1.4',
-                        'Jinja2>=2.10',
+      install_requires=['jinja2>=2.10',
+                        'pyverilog>=1.1.4',
                         'numpy>=1.14'],
       extras_require={
           'test': ['pytest>=3.2', 'pytest-pythonpath>=0.7'],

veriloggen/types/axi.py

@@ -2255,9 +2255,6 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
             self.wresp.bvalid(1)
         )
 
-        self.mem = self.m.Reg(
-            '_'.join(['', self.name, 'mem']), 8, vtypes.Int(2) ** self.mem_addrwidth)
-
         if memimg is None:
             if memimg_name is None:
                 memimg_name = '_'.join(['', self.name, 'memimg', '.out'])
@@ -2268,12 +2265,24 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
         elif isinstance(memimg, str):
             memimg_name = memimg
 
+            num_words = sum(1 for line in open(memimg, 'r'))
+            # resize mem_addrwidth according to the memimg size
+            self.mem_addrwidth = max(self.mem_addrwidth,
+                                     int(math.ceil(math.log(num_words, 2))))
+
         else:
             if memimg_datawidth is None:
                 memimg_datawidth = mem_datawidth
             if memimg_name is None:
                 memimg_name = '_'.join(['', self.name, 'memimg', '.out'])
-            to_memory_image(memimg_name, memimg, datawidth=memimg_datawidth)
+
+            num_words = to_memory_image(memimg_name, memimg, datawidth=memimg_datawidth)
+            # resize mem_addrwidth according to the memimg size
+            self.mem_addrwidth = max(self.mem_addrwidth,
+                                     int(math.ceil(math.log(num_words, 2))))
+
+        self.mem = self.m.Reg(
+            '_'.join(['', self.name, 'mem']), 8, vtypes.Int(2) ** self.mem_addrwidth)
 
         self.m.Initial(
             vtypes.Systask('readmemh', memimg_name, self.mem)
@@ -2582,6 +2591,9 @@ def to_memory_image(filename, array, length=None,
                 for v in values:
                     f.write(fmt % v)
 
+        num_lines = len(array) * num
+        return num_lines
+
     else:
         num = int(math.ceil(wordwidth / datawidth))
         mask = (2 ** datawidth) - 1
@@ -2602,6 +2614,9 @@ def to_memory_image(filename, array, length=None,
                     f.write(fmt % cat)
                     values = []
 
+        num_lines = len(array) // num
+        return num_lines
+
 
 def aligned_shape(shape, datawidth, mem_datawidth):
     aligned_shape = list(shape[:])