Merge branch 'feature_optimize_axim' into develop

Author: shtaxxx

examples/simulation_verilator/test_simulation_verilator.py

@@ -53,9 +53,6 @@ def blink(size):
     def body(size, offset):
         # narrow dma test
         myaxi.dma_read(myram0, 0, 0, size)
-
-        ### ???
-
         myaxi.dma_read(myram1, 0, 0, size)
         myaxi.dma_read(myram2, 0, 0, size)
         myaxi.dma_read(myram3, 0, 0, size)
@@ -83,8 +80,8 @@ def body(size, offset):
 
         laddr = 0
         gaddr = offset
-        myaxi.dma_write([myram0, myram1, myram2, myram3],
-                        laddr, gaddr, size)
+        myaxi.dma_write_packed([myram0, myram1, myram2, myram3],
+                               laddr, gaddr, size * 4)
         print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
 
         # write
@@ -106,15 +103,15 @@ def body(size, offset):
 
         laddr = 0
         gaddr = array_size + offset
-        myaxi.dma_write([myram0, myram1, myram2, myram3],
-                        laddr, gaddr, size)
+        myaxi.dma_write_packed([myram0, myram1, myram2, myram3],
+                               laddr, gaddr, size * 4)
         print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
 
         # read
         laddr = 0
         gaddr = offset
-        myaxi.dma_read([myram0, myram1, myram2, myram3],
-                       laddr, gaddr, size)
+        myaxi.dma_read_packed([myram0, myram1, myram2, myram3],
+                              laddr, gaddr, size * 4)
         print('dma_read:  [%d] <- [%d]' % (laddr, gaddr))
 
         for i in range(size):
@@ -148,8 +145,8 @@ def body(size, offset):
         # read
         laddr = 0
         gaddr = array_size + offset
-        myaxi.dma_read([myram0, myram1, myram2, myram3],
-                       laddr, gaddr, size)
+        myaxi.dma_read_packed([myram0, myram1, myram2, myram3],
+                              laddr, gaddr, size * 4)
         print('dma_read:  [%d] <- [%d]' % (laddr, gaddr))
 
         for i in range(size):

examples/stream_axi_stream_fifo_ipxact_ultra96v2_pynq/test_stream_axi_stream_fifo_ipxact.py

@@ -25,7 +25,9 @@ def mkLed(memory_datawidth=128):
                                   numbanks=numbanks)
     myram1 = vthread.MultibankRAM(m, 'myram1', clk, rst, datawidth, addrwidth,
                                   numbanks=numbanks)
-    myram = (myram0, myram1)
+
+    #myram = vthread.to_multibank_ram((myram0, myram1), keep_hierarchy=True)
+    myram = vthread.to_multibank_ram((myram0, myram1))
 
     all_ok = m.TmpReg(initval=0)
 
@@ -59,7 +61,7 @@ def body(size, offset):
 
         laddr = 0
         gaddr = offset
-        myaxi.dma_write(myram, laddr, gaddr, size)
+        myaxi.dma_write(myram, laddr, gaddr, size * 2 * numbanks)
         print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
 
         # write
@@ -71,13 +73,13 @@ def body(size, offset):
 
         laddr = 0
         gaddr = array_size + offset
-        myaxi.dma_write(myram, laddr, gaddr, size)
+        myaxi.dma_write(myram, laddr, gaddr, size * 2 * numbanks)
         print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
 
         # read
         laddr = 0
         gaddr = offset
-        myaxi.dma_read(myram, laddr, gaddr, size)
+        myaxi.dma_read(myram, laddr, gaddr, size * 2 * numbanks)
         print('dma_read:  [%d] <- [%d]' % (laddr, gaddr))
 
         for bank in range(numbanks):
@@ -94,7 +96,7 @@ def body(size, offset):
         # read
         laddr = 0
         gaddr = array_size + offset
-        myaxi.dma_read(myram, laddr, gaddr, size)
+        myaxi.dma_read(myram, laddr, gaddr, size * 2 * numbanks)
         print('dma_read:  [%d] <- [%d]' % (laddr, gaddr))
 
         for bank in range(numbanks):

examples/stream_axi_stream_fifo_ultra96v2_pynq/test_stream_axi_stream_fifo.py

@@ -23,7 +23,6 @@ def mkLed(memory_datawidth=128):
     myaxi = vthread.AXIM(m, 'myaxi', clk, rst, memory_datawidth)
 
     pack_size = memory_datawidth // datawidth
-
     rams = [vthread.MultibankRAM(m, 'myram%d' % i, clk, rst, datawidth, addrwidth,
                                  numbanks=pack_size)
             for i in range(numbanks)]
@@ -73,9 +72,7 @@ def body(size, offset):
 
         laddr = 0
         gaddr = offset
-        myram.dma_write_block(myaxi, laddr, gaddr,
-                              size // pack_size,
-                              block_size // pack_size)
+        myaxi.dma_write_block(myram, laddr, gaddr, size, block_size)
         print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
 
         # write
@@ -99,17 +96,13 @@ def body(size, offset):
 
         laddr = 0
         gaddr = array_size + offset
-        myram.dma_write_block(myaxi, laddr, gaddr,
-                              size // pack_size,
-                              block_size // pack_size)
+        myaxi.dma_write_block(myram, laddr, gaddr, size, block_size)
         print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
 
         # read
         laddr = 0
         gaddr = offset
-        myram.dma_read_block(myaxi, laddr, gaddr,
-                             size // pack_size,
-                             block_size // pack_size)
+        myaxi.dma_read_block(myram, laddr, gaddr, size, block_size)
         print('dma_read:  [%d] <- [%d]' % (laddr, gaddr))
 
         count = 0
@@ -136,8 +129,7 @@ def body(size, offset):
         # read
         laddr = 0
         gaddr = array_size + offset
-        myram.dma_read_block(myaxi, laddr, gaddr, size //
-                             pack_size, block_size // pack_size)
+        myaxi.dma_read_block(myram, laddr, gaddr, size, block_size)
         print('dma_read:  [%d] <- [%d]' % (laddr, gaddr))
 
         count = 0
@@ -187,7 +179,7 @@ def mkTest(memimg_name=None, memory_datawidth=128):
                      params=m.connect_params(led),
                      ports=m.connect_ports(led))
 
-    #simulation.setup_waveform(m, uut)
+    # simulation.setup_waveform(m, uut)
     simulation.setup_clock(m, clk, hperiod=5)
     init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
 

examples/thread_embedded_verilog_ipxact/test_thread_embedded_verilog_ipxact.py

@@ -3,16 +3,16 @@
 
 import os
 import veriloggen
-import thread_multibank_ram_dma
+import thread_axi_dma
 
 
 def test(request):
     veriloggen.reset()
 
     simtype = request.config.getoption('--sim')
 
-    rslt = thread_multibank_ram_dma.run(filename=None, simtype=simtype,
-                                        outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
+    rslt = thread_axi_dma.run(filename=None, simtype=simtype,
+                              outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
 
     verify_rslt = rslt.splitlines()[-1]
     assert(verify_rslt == '# verify: PASSED')