A new test case is added: ternary operator

Author: shtaxxx

sample/tests/cond/Makefile

@@ -0,0 +1,39 @@
+TARGET=led.py
+TEST=test_led.py
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv $(TEST)
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out tmp.v uut.vcd
+
+.PHONY: sim
+sim:
+	iverilog -Wall tmp.v
+	./a.out
+
+.PHONY: view
+view:
+	gtkwave --giga uut.vcd &

sample/tests/cond/led.py

@@ -0,0 +1,60 @@
+import sys
+import os
+from veriloggen import *
+
+def mkLed():
+    m = Module('blinkled')
+    width = m.Parameter('WIDTH', 8)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    led = m.OutputReg('LED', width)
+    count = m.Reg('count', 32)
+
+    m.Always(Posedge(clk))(
+        If(rst)(
+            count(0)
+        ).Else(
+            count( Cond(count==1023, 0, count + 1) )
+        ))
+    
+    m.Always(Posedge(clk))(
+        If(rst)(
+            led(0)
+        ).Else(
+            led( Cond(count==1024-1, led+1, led) )
+        ))
+    
+    return m
+
+def mkTest():
+    m = Module('test')
+    
+    # target instance
+    led = mkLed()
+    
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+    
+    clk = ports['CLK']
+    rst = ports['RST']
+    
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+    
+    lib.simulation.setup_waveform(m, uut, m.get_vars())
+    lib.simulation.setup_clock(m, clk, hperiod=5)
+    init = lib.simulation.setup_reset(m, rst, m.make_reset(), period=100)
+    
+    init.add(
+        Delay(1000 * 100),
+        Systask('finish'),
+    )
+
+    return m
+    
+if __name__ == '__main__':
+    test = mkTest()
+    verilog = test.to_verilog('tmp.v')
+    print(verilog)

sample/tests/cond/test_led.py

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+import led
+
+expected_verilog = """
+module test #
+(
+  parameter WIDTH = 8
+)
+(
+);
+
+  reg CLK;
+  reg RST;
+  wire [(WIDTH - 1):0] LED;
+
+  blinkled
+  #(
+    .WIDTH(WIDTH)
+  )
+  uut
+  (
+    .CLK(CLK),
+    .RST(RST),
+    .LED(LED)
+  );
+
+  initial begin
+    $dumpfile("uut.vcd");
+    $dumpvars(0, uut, CLK, RST, LED);
+  end
+
+  initial begin
+    CLK = 0;
+    forever begin
+      #5 CLK = (!CLK);
+    end
+  end
+
+  initial begin
+    RST = 0;
+    #100;
+    RST = 1;
+    #100;
+    RST = 0;
+    #100000;
+    $finish;
+  end
+endmodule
+
+module blinkled #
+  ( 
+   parameter WIDTH = 8
+  )
+  ( 
+   input CLK, 
+   input RST,
+   output reg [WIDTH-1:0] LED
+  );
+  reg [32-1:0] count;
+  always @(posedge CLK) begin
+    if(RST) begin
+      count <= 0;
+    end else begin
+      count <= (count == 1023)? 0 : count + 1;
+    end
+  end
+  always @(posedge CLK) begin
+    if(RST) begin
+      LED <= 0;
+    end else begin
+      LED <= (count == 1023)? LED + 1 : LED;
+    end
+  end
+endmodule
+"""
+
+def test_led():
+    test_module = led.mkTest()
+    code = test_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(expected_code == code)

sample/tests/cond/veriloggen

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+../../../veriloggen