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Dump mode of Stream is enhanced for RAM read/write
1 parent 7d61e71 commit 7c7a19b

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3 files changed

+157
-27
lines changed

3 files changed

+157
-27
lines changed

tests/extension/thread_/stream_dump_selective/thread_stream_dump_selective.py

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,8 @@ def mkLed():
3232
c.dump = True
3333
strm.sink(c, 'c')
3434

35+
ram_c.dump = True
36+
3537
def comp_stream(size, offset):
3638
strm.set_source('a', ram_a, offset, size)
3739
strm.set_source('b', ram_b, offset, size)

veriloggen/stream/stream.py

Lines changed: 35 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -231,21 +231,23 @@ def implement(self, m=None, clock=None, reset=None, aswire=None, seq_name=None):
231231
def add_dump(self, m, seq, input_vars, output_vars, all_vars):
232232
dump_enable_name = '_stream_dump_enable_%d' % self.object_id
233233
dump_enable = m.Reg(dump_enable_name, initval=0)
234-
dump_iter_name = '_stream_dump_iter_%d' % self.object_id
235-
dump_iter = m.Reg(dump_iter_name, 32, initval=0)
234+
dump_step_name = '_stream_dump_step_%d' % self.object_id
235+
dump_step = m.Reg(dump_step_name, 32, initval=0, signed=True)
236236

237+
self.dump_step = dump_step
237238
self.dump_enable = dump_enable
238239

239240
pipeline_depth = self.pipeline_depth()
240-
log_pipeline_depth = int(math.ceil(math.log(pipeline_depth, 10)))
241+
log_pipeline_depth = max(
242+
int(math.ceil(math.log(pipeline_depth, 10))), 1)
241243

242244
seq(
243-
dump_iter(0)
245+
dump_step(0)
244246
)
245247

246248
for i in range(pipeline_depth + 1):
247249
seq.If(seq.Prev(dump_enable, i))(
248-
dump_iter.inc()
250+
dump_step.inc()
249251
)
250252

251253
def get_name(obj):
@@ -257,7 +259,9 @@ def get_name(obj):
257259

258260
longest_name_len = 0
259261
for input_var in sorted(input_vars, key=lambda x: x.object_id):
260-
if not (self.dump_mode == 'all' or self.dump_mode == 'input' or
262+
if not (self.dump_mode == 'all' or
263+
self.dump_mode == 'stream' or
264+
self.dump_mode == 'input' or
261265
self.dump_mode == 'inout' or
262266
(self.dump_mode == 'selective' and
263267
hasattr(input_var, 'dump') and input_var.dump)):
@@ -271,6 +275,7 @@ def get_name(obj):
271275
if x.end_stage is None else
272276
(x.end_stage, x.object_id)):
273277
if not (self.dump_mode == 'all' or
278+
self.dump_mode == 'stream' or
274279
(self.dump_mode == 'selective' and
275280
hasattr(var, 'dump') and var.dump)):
276281
continue
@@ -280,7 +285,9 @@ def get_name(obj):
280285
longest_name_len = max(longest_name_len, length)
281286

282287
for output_var in sorted(output_vars, key=lambda x: x.object_id):
283-
if not (self.dump_mode == 'all' or self.dump_mode == 'output' or
288+
if not (self.dump_mode == 'all' or
289+
self.dump_mode == 'stream' or
290+
self.dump_mode == 'output' or
284291
self.dump_mode == 'inout' or
285292
(self.dump_mode == 'selective' and
286293
hasattr(output_var, 'dump') and output_var.dump)):
@@ -325,7 +332,9 @@ def get_name(obj):
325332

326333
enables = []
327334
for input_var in sorted(input_vars, key=lambda x: x.object_id):
328-
if not (self.dump_mode == 'all' or self.dump_mode == 'input' or
335+
if not (self.dump_mode == 'all' or
336+
self.dump_mode == 'stream' or
337+
self.dump_mode == 'input' or
329338
self.dump_mode == 'inout' or
330339
(self.dump_mode == 'selective' and
331340
hasattr(input_var, 'dump') and input_var.dump)):
@@ -336,14 +345,15 @@ def get_name(obj):
336345
name = get_name(input_var.sig_data)
337346
name_alignment = ' ' * (longest_name_len - len(name) -
338347
len('(in) '))
339-
fmt = ''.join(['<', self.name, '> (iter %d) ',
340-
'(stage %', str(log_pipeline_depth), 'd, age %d) ', '(in) ',
348+
fmt = ''.join(['<', self.name, ' step:%d, ',
349+
'stage:%', str(
350+
log_pipeline_depth), 'd, age:%d> (in) ',
341351
name_alignment, name, ' = ', vfmt])
342352

343353
stage = input_var.end_stage if input_var.end_stage is not None else 0
344354
enable = seq.Prev(dump_enable, stage)
345355
enables.append(enable)
346-
age = seq.Prev(dump_iter, stage)
356+
age = seq.Prev(dump_step, stage)
347357

348358
if input_var.point == 0:
349359
sig_data = input_var.sig_data
@@ -352,13 +362,14 @@ def get_name(obj):
352362
1.0 * (2 ** input_var.point))
353363

354364
seq.If(enable)(
355-
vtypes.Display(fmt, dump_iter, stage, age, sig_data)
365+
vtypes.Display(fmt, dump_step, stage, age, sig_data)
356366
)
357367

358368
for var in sorted(all_vars, key=lambda x: (-1, x.object_id)
359369
if x.end_stage is None else
360370
(x.end_stage, x.object_id)):
361371
if not (self.dump_mode == 'all' or
372+
self.dump_mode == 'stream' or
362373
(self.dump_mode == 'selective' and
363374
hasattr(var, 'dump') and var.dump)):
364375
continue
@@ -369,13 +380,13 @@ def get_name(obj):
369380
name_alignment = ' ' * (longest_name_len - len(name))
370381
stage = var.end_stage if var.end_stage is not None else 0
371382

372-
fmt = ''.join(['<', self.name, '> (iter %d) ',
373-
'(stage %', str(log_pipeline_depth), 'd, age %d) ',
383+
fmt = ''.join(['<', self.name, ' step:%d, ',
384+
'stage:%', str(log_pipeline_depth), 'd, age:%d> ',
374385
name_alignment, name, ' = ', vfmt])
375386

376387
enable = seq.Prev(dump_enable, stage)
377388
enables.append(enable)
378-
age = seq.Prev(dump_iter, stage)
389+
age = seq.Prev(dump_step, stage)
379390

380391
if var.point == 0:
381392
sig_data = var.sig_data
@@ -384,11 +395,13 @@ def get_name(obj):
384395
1.0 * (2 ** var.point))
385396

386397
seq.If(enable)(
387-
vtypes.Display(fmt, dump_iter, stage, age, sig_data)
398+
vtypes.Display(fmt, dump_step, stage, age, sig_data)
388399
)
389400

390401
for output_var in sorted(output_vars, key=lambda x: x.object_id):
391-
if not (self.dump_mode == 'all' or self.dump_mode == 'output' or
402+
if not (self.dump_mode == 'all' or
403+
self.dump_mode == 'stream' or
404+
self.dump_mode == 'output' or
392405
self.dump_mode == 'inout' or
393406
(self.dump_mode == 'selective' and
394407
hasattr(output_var, 'dump') and output_var.dump)):
@@ -399,14 +412,15 @@ def get_name(obj):
399412
name = get_name(output_var.output_sig_data)
400413
name_alignment = ' ' * (longest_name_len - len(name) -
401414
len('(out) '))
402-
fmt = ''.join(['<', self.name, '> (iter %d) ',
403-
'(stage %', str(log_pipeline_depth), 'd, age %d) ', '(out) ',
415+
fmt = ''.join(['<', self.name, ' step:%d, ',
416+
'stage:%', str(
417+
log_pipeline_depth), 'd, age:%d> (out) ',
404418
name_alignment, name, ' = ', vfmt])
405419

406420
stage = output_var.end_stage if output_var.end_stage is not None else 0
407421
enable = seq.Prev(dump_enable, stage)
408422
enables.append(enable)
409-
age = seq.Prev(dump_iter, stage)
423+
age = seq.Prev(dump_step, stage)
410424

411425
if output_var.point == 0:
412426
sig_data = output_var.output_sig_data
@@ -415,13 +429,7 @@ def get_name(obj):
415429
1.0 * (2 ** output_var.point))
416430

417431
seq.If(enable)(
418-
vtypes.Display(fmt, dump_iter, stage, age, sig_data)
419-
)
420-
421-
if enables:
422-
seq.If(vtypes.Ors(*enables))(
423-
vtypes.Display(''.join(['<', self.name, '> (iter %d) ', '--------']),
424-
dump_iter)
432+
vtypes.Display(fmt, dump_step, stage, age, sig_data)
425433
)
426434

427435
# -------------------------------------------------------------------------

veriloggen/thread/stream.py

Lines changed: 120 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1180,6 +1180,72 @@ def _setup_source_ram(self, ram, var, port, set_cond):
11801180
var.source_ram_rvalid(1)
11811181
)
11821182

1183+
if (self.dump and
1184+
(self.dump_mode == 'all' or
1185+
self.dump_mode == 'ram' or
1186+
(self.dump_mode == 'selective' and
1187+
hasattr(ram, 'dump') and ram.dump))):
1188+
self._setup_source_ram_dump(ram, var, renable, d)
1189+
1190+
def _setup_source_ram_dump(self, ram, var, read_enable, read_data):
1191+
pipeline_depth = self.pipeline_depth()
1192+
log_pipeline_depth = max(
1193+
int(math.ceil(math.log(pipeline_depth, 10))), 1)
1194+
1195+
addr_base = (ram.dump_addr_base if hasattr(ram, 'dump_addr_base') else
1196+
self.dump_base)
1197+
addr_base_char = ('b' if addr_base == 2 else
1198+
'o' if addr_base == 8 else
1199+
'd' if addr_base == 10 else
1200+
'x')
1201+
addr_prefix = ('0b' if addr_base == 2 else
1202+
'0o' if addr_base == 8 else
1203+
' ' if addr_base == 10 else
1204+
'0x')
1205+
addr_vfmt = ''.join([addr_prefix, '%', addr_base_char])
1206+
1207+
data_base = (ram.dump_data_base if hasattr(ram, 'dump_data_base') else
1208+
self.dump_base)
1209+
data_base_char = ('b' if data_base == 2 else
1210+
'o' if data_base == 8 else
1211+
'd' if (data_base == 10 and
1212+
(not hasattr(ram, 'point') or ram.point == 0)) else
1213+
'f' if (data_base == 10 and
1214+
hasattr(ram, 'point') and ram.point > 0) else
1215+
'x')
1216+
data_prefix = ('0b' if data_base == 2 else
1217+
'0o' if data_base == 8 else
1218+
' ' if data_base == 10 else
1219+
'0x')
1220+
data_vfmt = ''.join([data_prefix, '%', data_base_char])
1221+
1222+
name = ram.name
1223+
fmt = ''.join(['(', self.name, ' step:%d, ',
1224+
'read, ', ' ' * (log_pipeline_depth + 2),
1225+
'age:%d) ', name,
1226+
'[', addr_vfmt, '] = ', data_vfmt])
1227+
1228+
dump_ram_step_name = ('_stream_dump_ram_step_%d_%s' %
1229+
(self.object_id, name))
1230+
dump_ram_step = self.module.Reg(dump_ram_step_name, 32,
1231+
initval=0, signed=True)
1232+
1233+
enable = self.seq.Prev(read_enable, 2)
1234+
age = dump_ram_step + 1
1235+
addr = self.seq.Prev(var.source_ram_raddr, 2)
1236+
data = read_data
1237+
1238+
self.seq(
1239+
dump_ram_step(-1)
1240+
)
1241+
self.seq.If(enable)(
1242+
dump_ram_step.inc()
1243+
)
1244+
1245+
self.seq.If(enable)(
1246+
vtypes.Display(fmt, dump_ram_step, age, addr, data)
1247+
)
1248+
11831249
def _synthesize_set_source(self, var, name):
11841250
if var.source_fsm is not None:
11851251
return
@@ -1556,6 +1622,60 @@ def _setup_sink_ram(self, ram, var, port, set_cond):
15561622
ram.write_rtl(var.sink_ram_waddr, var.sink_ram_wdata,
15571623
port=port, cond=wenable)
15581624

1625+
if (self.dump and
1626+
(self.dump_mode == 'all' or
1627+
self.dump_mode == 'ram' or
1628+
(self.dump_mode == 'selective' and
1629+
hasattr(ram, 'dump') and ram.dump))):
1630+
self._setup_sink_ram_dump(ram, var, wenable)
1631+
1632+
def _setup_sink_ram_dump(self, ram, var, write_enable):
1633+
pipeline_depth = self.pipeline_depth()
1634+
log_pipeline_depth = max(
1635+
int(math.ceil(math.log(pipeline_depth, 10))), 1)
1636+
1637+
addr_base = (ram.dump_addr_base if hasattr(ram, 'dump_addr_base') else
1638+
self.dump_base)
1639+
addr_base_char = ('b' if addr_base == 2 else
1640+
'o' if addr_base == 8 else
1641+
'd' if addr_base == 10 else
1642+
'x')
1643+
addr_prefix = ('0b' if addr_base == 2 else
1644+
'0o' if addr_base == 8 else
1645+
' ' if addr_base == 10 else
1646+
'0x')
1647+
addr_vfmt = ''.join([addr_prefix, '%', addr_base_char])
1648+
1649+
data_base = (ram.dump_data_base if hasattr(ram, 'dump_data_base') else
1650+
self.dump_base)
1651+
data_base_char = ('b' if data_base == 2 else
1652+
'o' if data_base == 8 else
1653+
'd' if (data_base == 10 and
1654+
(not hasattr(ram, 'point') or ram.point == 0)) else
1655+
'f' if (data_base == 10 and
1656+
hasattr(ram, 'point') and ram.point > 0) else
1657+
'x')
1658+
data_prefix = ('0b' if data_base == 2 else
1659+
'0o' if data_base == 8 else
1660+
' ' if data_base == 10 else
1661+
'0x')
1662+
data_vfmt = ''.join([data_prefix, '%', data_base_char])
1663+
1664+
name = ram.name
1665+
fmt = ''.join(['(', self.name, ' step:%d, ',
1666+
'write, ', ' ' * (log_pipeline_depth + 1),
1667+
'age:%d) ', name,
1668+
'[', addr_vfmt, '] = ', data_vfmt])
1669+
1670+
enable = var.sink_ram_wenable
1671+
age = self.seq.Prev(self.dump_step, pipeline_depth + 1)
1672+
addr = var.sink_ram_waddr
1673+
data = var.sink_ram_wdata
1674+
1675+
self.seq.If(enable)(
1676+
vtypes.Display(fmt, self.dump_step, age, addr, data)
1677+
)
1678+
15591679
def _synthesize_set_sink(self, var, name):
15601680
if var.sink_fsm is not None:
15611681
return

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