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Updated the test codes for verilator simulation.
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3 files changed

+9
-63
lines changed

3 files changed

+9
-63
lines changed

examples/simulation_verilator/test_simulation_verilator.py

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2549,19 +2549,17 @@
25492549
int main(int argc, char** argv)
25502550
{
25512551
Verilated::commandArgs(argc, argv);
2552-
2552+
25532553
Top *top = new Top();
25542554
2555-
#ifdef TRACE
2555+
#ifdef TRACE
25562556
Verilated::traceEverOn(true);
25572557
VerilatedVcdC* tfp = new VerilatedVcdC;
25582558
top->trace(tfp, 99);
25592559
tfp->open("simulation_verilator.vcd");
25602560
#endif
25612561
top->io_CLK = 0;
2562-
25632562
top->io_RST = 0;
2564-
25652563
25662564
// input initialization
25672565
@@ -2579,8 +2577,8 @@
25792577
// update input
25802578
25812579
top->eval();
2582-
2583-
#ifdef TRACE
2580+
2581+
#ifdef TRACE
25842582
tfp->dump(main_time);
25852583
#endif
25862584
@@ -2592,10 +2590,10 @@
25922590
main_time += TIME_STEP;
25932591
}
25942592
2595-
#ifdef TRACE
2593+
#ifdef TRACE
25962594
tfp->close();
25972595
#endif
2598-
2596+
25992597
top->final();
26002598
26012599
return 0;

tests/simulation/simulator/verilator/simulation_simulator_verilator.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -30,7 +30,7 @@ def mkLed():
3030
led.inc()
3131
)
3232

33-
seq(
33+
seq.If(led < 4)(
3434
Systask('display', "LED:%d count:%d", led, count)
3535
)
3636

@@ -64,7 +64,7 @@ def mkTest():
6464
test = mkTest()
6565

6666
sim = simulation.Simulator(test, sim='verilator')
67-
rslt = sim.run(sim_time=1000 * 2 - 5, outputfile='out')
67+
rslt = sim.run(sim_time=10000)
6868
print(rslt)
6969

7070
# sim.view_waveform()

tests/simulation/simulator/verilator/test_simulation_simulator_verilator.py

Lines changed: 1 addition & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -143,64 +143,12 @@
143143
LED: 3 count: 29
144144
LED: 3 count: 30
145145
LED: 3 count: 31
146-
LED: 4 count: 0
147-
LED: 4 count: 1
148-
LED: 4 count: 2
149-
LED: 4 count: 3
150-
LED: 4 count: 4
151-
LED: 4 count: 5
152-
LED: 4 count: 6
153-
LED: 4 count: 7
154-
LED: 4 count: 8
155-
LED: 4 count: 9
156-
LED: 4 count: 10
157-
LED: 4 count: 11
158-
LED: 4 count: 12
159-
LED: 4 count: 13
160-
LED: 4 count: 14
161-
LED: 4 count: 15
162-
LED: 4 count: 16
163-
LED: 4 count: 17
164-
LED: 4 count: 18
165-
LED: 4 count: 19
166-
LED: 4 count: 20
167-
LED: 4 count: 21
168-
LED: 4 count: 22
169-
LED: 4 count: 23
170-
LED: 4 count: 24
171-
LED: 4 count: 25
172-
LED: 4 count: 26
173-
LED: 4 count: 27
174-
LED: 4 count: 28
175-
LED: 4 count: 29
176-
LED: 4 count: 30
177-
LED: 4 count: 31
178-
LED: 5 count: 0
179-
LED: 5 count: 1
180-
LED: 5 count: 2
181-
LED: 5 count: 3
182-
LED: 5 count: 4
183-
LED: 5 count: 5
184-
LED: 5 count: 6
185-
LED: 5 count: 7
186-
LED: 5 count: 8
187-
LED: 5 count: 9
188-
LED: 5 count: 10
189-
LED: 5 count: 11
190-
LED: 5 count: 12
191-
LED: 5 count: 13
192-
LED: 5 count: 14
193-
LED: 5 count: 15
194-
LED: 5 count: 16
195-
LED: 5 count: 17
196-
LED: 5 count: 18
197-
LED: 5 count: 19
198146
"""
199147

200148

201149
def test():
202150
vg.reset()
203151
test_module = simulation_simulator_verilator.mkTest()
204152
sim = vg.simulation.Simulator(test_module, sim='verilator')
205-
rslt = sim.run(sim_time=1000 * 2 - 5)
153+
rslt = sim.run(sim_time=10000)
206154
assert(expected_rslt == rslt)

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