sample/led with testbench.

Author: shtaxxx

sample/led/Makefile

@@ -27,4 +27,13 @@ check:
 
 .PHONY: clean
 clean:
-	rm -rf *.pyc __pycache__ parsetab.py *.out
+	rm -rf *.pyc __pycache__ parsetab.py *.out tmp.v uut.vcd
+
+.PHONY: sim
+sim:
+	iverilog -Wall tmp.v
+	./a.out
+
+.PHONY: view
+view:
+	gtkwave --giga uut.vcd &

sample/led/led.py

@@ -32,7 +32,35 @@ def mkLed():
 
     return m
 
-if __name__ == '__main__':
+def mkTest():
+    m = Module('test')
+    
+    # target instance
     led = mkLed()
-    verilog = led.to_verilog()
+    
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+    
+    clk = ports['CLK']
+    rst = ports['RST']
+    
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+    
+    lib.simulation.setup_waveform(m, uut, m.get_vars())
+    lib.simulation.setup_clock(m, clk, hperiod=5)
+    init = lib.simulation.setup_reset(m, rst, m.reset(), period=100)
+    
+    init.add(
+        Delay(1000 * 100),
+        Systask('finish'),
+    )
+
+    return m
+    
+if __name__ == '__main__':
+    test = mkTest()
+    verilog = test.to_verilog('tmp.v')
     print(verilog)

sample/led/test_led.py

@@ -1,6 +1,51 @@
 import led
 
 expected_verilog = """
+module test #
+(
+  parameter WIDTH = 8
+)
+(
+);
+
+  reg CLK;
+  reg RST;
+  wire [(WIDTH - 1):0] LED;
+
+  blinkled
+  #(
+    .WIDTH(WIDTH)
+  )
+  uut
+  (
+    .CLK(CLK),
+    .RST(RST),
+    .LED(LED)
+  );
+
+  initial begin
+    $dumpfile("uut.vcd");
+    $dumpvars(0, uut, CLK, RST, LED);
+  end
+
+  initial begin
+    CLK = 0;
+    forever begin
+      #5 CLK = (!CLK);
+    end
+  end
+
+  initial begin
+    RST = 0;
+    #100;
+    RST = 1;
+    #100;
+    RST = 0;
+    #100000;
+    $finish;
+  end
+endmodule
+
 module blinkled #
   ( 
    parameter WIDTH = 8
@@ -35,8 +80,8 @@
 """
 
 def test_led():
-    led_module = led.mkLed()
-    led_code = led_module.to_verilog()
+    test_module = led.mkTest()
+    code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser
     from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
@@ -45,4 +90,4 @@ def test_led():
     codegen = ASTCodeGenerator()
     expected_code = codegen.visit(expected_ast)
 
-    assert(expected_code == led_code)
+    assert(expected_code == code)