stream_axi_stream_aync is using non-blocking read/write to AXI-Stream

Author: shtaxxx

tests/extension/thread_/stream_axi_stream_async/Makefile

@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

tests/extension/thread_/stream_axi_stream_async/test_thread_stream_axi_stream_async.py

@@ -0,0 +1,18 @@
+from __future__ import absolute_import
+from __future__ import print_function
+
+import os
+import veriloggen
+import thread_stream_axi_stream_async
+
+
+def test(request):
+    veriloggen.reset()
+
+    simtype = request.config.getoption('--sim')
+
+    rslt = thread_stream_axi_stream_async.run(filename=None, simtype=simtype,
+                                              outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
+
+    verify_rslt = rslt.splitlines()[-1]
+    assert(verify_rslt == '# verify: PASSED')

tests/extension/thread_/stream_axi_stream_async/thread_stream_axi_stream_async.py

@@ -0,0 +1,86 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+import veriloggen.thread as vthread
+import veriloggen.types.axi as axi
+
+
+def mkLed():
+    m = Module('blinkled')
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+
+    datawidth = 32
+    addrwidth = 10
+
+    axi_a = vthread.AXIStreamIn(m, 'axi_a', clk, rst, datawidth, with_last=True,
+                                enable_async=True)
+    axi_b = vthread.AXIStreamIn(m, 'axi_b', clk, rst, datawidth, with_last=True,
+                                enable_async=True)
+    axi_c = vthread.AXIStreamOut(m, 'axi_c', clk, rst, datawidth, with_last=True,
+                                 enable_async=True)
+
+    saxi = vthread.AXISLiteRegister(m, 'saxi', clk, rst, datawidth)
+
+    ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth, numports=2)
+    ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth, numports=2)
+    ram_c = vthread.RAM(m, 'ram_c', clk, rst, datawidth, addrwidth, numports=2)
+
+    strm = vthread.Stream(m, 'mystream', clk, rst)
+    a = strm.source('a')
+    b = strm.source('b')
+    c = a + b
+    strm.sink(c, 'c')
+
+    def comp_stream(size, offset):
+        strm.set_source('a', ram_a, offset, size)
+        strm.set_source('b', ram_b, offset, size)
+        strm.set_sink('c', ram_c, offset, size)
+        strm.run()
+        strm.join()
+
+    def comp():
+        while True:
+            saxi.wait_flag(0, value=1, resetvalue=0)
+            saxi.write(1, 1)  # set busy
+            size = saxi.read(2)
+            offset = 0
+
+            axi_a.read_stream_async(ram_a, offset, size, port=1)  # non-blocking read
+            axi_b.read_stream_async(ram_b, offset, size, port=1)  # non-blocking read
+            axi_a.wait_read_stream()  # wait
+            axi_b.wait_read_stream()  # wait
+            comp_stream(size, offset)
+            axi_c.write_stream(ram_c, offset, size, port=1)  # non-blocking write
+            axi_c.wait_write_stream()  # wait
+
+            saxi.write(1, 0)  # unset busy
+
+        vthread.finish()
+
+    th = vthread.Thread(m, 'th_comp', clk, rst, comp)
+    fsm = th.start()
+
+    return m
+
+
+def run(filename='tmp.v', simtype='iverilog', outputfile=None):
+
+    test = mkLed()
+
+    if filename is not None:
+        test.to_verilog(filename)
+
+    return '# verify: PASSED'
+
+
+if __name__ == '__main__':
+    rslt = run(filename='tmp.v')
+    print(rslt)

veriloggen/thread/axi.py

@@ -2330,7 +2330,7 @@ def _synthesize_read_fsm_same(self, ram, port, ram_method, ram_datawidth):
             rest_size.dec()
         )
 
-        fsm.If(valid, rest_size <= 1).goto_next()
+        fsm.If(valid, vtypes.Ors(rest_size <= 1, last)).goto_next()
 
         for _ in range(self.num_data_delay):
             fsm.goto_next()
@@ -2393,7 +2393,7 @@ def _synthesize_read_fsm_narrow(self, ram, port, ram_method, ram_datawidth):
                 wvalid(0),
                 pack_count.inc()
             )
-            fsm.If(valid_cond, pack_count == pack_size - 1)(
+            fsm.If(valid_cond, vtypes.Ors(pack_count == pack_size - 1, last))(
                 wdata(vtypes.Cat(data, wdata[self.datawidth:ram_datawidth])),
                 wvalid(1),
                 pack_count(0)
@@ -2437,7 +2437,7 @@ def _synthesize_read_fsm_narrow(self, ram, port, ram_method, ram_datawidth):
                                 int(math.ceil(math.log(pack_size, 2))), initval=0)
         self.read_narrow_pack_counts[pack_size] = pack_count
 
-        data, valid, last = self.read_data(cond=fsm)
+        data, last, _id, user, dest, valid = self.read_data(cond=fsm)
         self.read_narrow_data_wires[pack_size] = data
         self.read_narrow_valid_wires[pack_size] = valid
 
@@ -2451,7 +2451,7 @@ def _synthesize_read_fsm_narrow(self, ram, port, ram_method, ram_datawidth):
             wvalid(0),
             pack_count.inc()
         )
-        fsm.If(valid_cond, pack_count == pack_size - 1)(
+        fsm.If(valid_cond, vtypes.Ors(pack_count == pack_size - 1, last))(
             wdata(vtypes.Cat(data, wdata[self.datawidth:ram_datawidth])),
             wvalid(1),
             pack_count(0)
@@ -2460,7 +2460,7 @@ def _synthesize_read_fsm_narrow(self, ram, port, ram_method, ram_datawidth):
             rest_size.dec()
         )
 
-        fsm.If(valid, rest_size <= 1).goto_next()
+        fsm.If(valid, vtypes.Ors(rest_size <= 1, last)).goto_next()
 
         for _ in range(self.num_data_delay):
             fsm.goto_next()
@@ -2572,19 +2572,25 @@ def _synthesize_read_fsm_wide(self, ram, port, ram_method, ram_datawidth):
         self.read_wide_pack_counts[pack_size] = pack_count
 
         cond = vtypes.Ands(fsm.here, pack_count == 0)
-        data, valid, last = self.read_data(cond=cond)
+        data, last, _id, user, dest, valid = self.read_data(cond=fsm)
         self.read_wide_data_wires[pack_size] = data
         self.read_wide_valid_wires[pack_size] = valid
 
         valid_cond = vtypes.Ands(valid, self.read_op_sel == op_id)
         stay_cond = self.read_op_sel == op_id
 
+        wlast = self.m.Reg('_'.join(['', self.name,
+                                     'read_wide', str(pack_size),
+                                     'wlast']),
+                           initval=0)
+
         fsm.Delay(1)(
             wvalid(0)
         )
         fsm.If(pack_count == 0, valid_cond)(
             wdata(data),
             wvalid(1),
+            wlast(last),
             pack_count.inc()
         )
         fsm.If(pack_count > 0, stay_cond)(
@@ -2601,7 +2607,7 @@ def _synthesize_read_fsm_wide(self, ram, port, ram_method, ram_datawidth):
         )
 
         fsm.If(pack_count == pack_size - 1,
-               rest_size == 0).goto_next()
+               vtypes.Ors(rest_size == 0, wlast)).goto_next()
 
         for _ in range(self.num_data_delay):
             fsm.goto_next()