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remove reset input from RandXorshift class
1 parent bf6c73f commit 71744ba

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2 files changed

+8
-22
lines changed

2 files changed

+8
-22
lines changed

tests/extension/thread_/stream_rand_xorshift/thread_stream_rand_xorshift.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,7 @@ def mkLed():
2626
ram_c = vthread.RAM(m, 'ram_c', clk, rst, datawidth, addrwidth)
2727

2828
strm = vthread.Stream(m, 'mystream', clk, rst)
29-
rand_hard = strm.RandXorshift(initval=initval)
29+
rand_hard = strm.RandXorshift(reg_initval=initval)
3030
a = strm.source('a')
3131
b = strm.source('b')
3232
c = a + b - a - b + rand_hard

veriloggen/stream/stypes.py

Lines changed: 7 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -3632,12 +3632,14 @@ def _implement(self, m, seq, svalid=None, senable=None):
36323632

36333633
class RandXorshift(_Accumulator):
36343634

3635-
def __init__(self, initval=0x12345678, dependency=None, enable=None, reset=None,
3636-
reg_initval=None, width=32):
3635+
def __init__(self, reg_initval=0x12345678, dependency=None, enable=None, width=32):
3636+
36373637
right = 0
36383638
size = None
36393639
interval = None
3640+
initval = None
36403641
offset = None
3642+
reset = None
36413643
signed = False
36423644

36433645
_Accumulator.__init__(self, right, size, interval, initval, offset,
@@ -3649,7 +3651,6 @@ def _implement(self, m, seq, svalid=None, senable=None):
36493651
raise ValueError("Latency mismatch '%d' vs '%s'" %
36503652
(self.latency, 1))
36513653

3652-
initval_data = self.initval.sig_data
36533654
width = self.get_width()
36543655
signed = self.get_signed()
36553656

@@ -3664,39 +3665,24 @@ def _implement(self, m, seq, svalid=None, senable=None):
36643665
self.sig_data = data
36653666

36663667
enabledata = self.enable.sig_data if self.enable is not None else None
3667-
resetdata = self.reset.sig_data if self.reset is not None else None
3668-
3669-
reset_cond = m.Wire(self.name('reset_cond'))
3670-
if self.reset is not None:
3671-
reset_cond.assign(resetdata)
3672-
current_randval = m.WireLike(randval, name=self.name('current_count'))
3673-
current_randval.assign(vtypes.Mux(reset_cond, initval_data, randval))
3674-
else:
3675-
reset_cond.assign(0)
3676-
current_randval = randval
36773668

36783669
if width == 32:
3679-
next_value = current_randval ^ (current_randval << 13)
3670+
next_value = randval ^ (randval << 13)
36803671
next_value = next_value ^ (next_value >> 17)
36813672
next_value = next_value ^ (next_value << 5)
36823673
elif width == 64:
3683-
next_value = current_randval ^ (current_randval << 13)
3674+
next_value = randval ^ (randval << 13)
36843675
next_value = next_value ^ (next_value >> 7)
36853676
next_value = next_value ^ (next_value << 17)
36863677
else:
36873678
raise ValueError("Invalid width value '%d', please specify 32 or 64" % width)
36883679

36893680
enable_cond = _and_vars(svalid, senable)
36903681

3691-
if self.reset is not None:
3692-
enable_reset_cond = _and_vars(enable_cond, reset_cond)
3693-
seq(data(initval_data), cond=enable_reset_cond)
3694-
3695-
seq(data(current_randval), cond=enable_cond)
3696-
36973682
if self.enable is not None:
36983683
enable_cond = _and_vars(enable_cond, enabledata)
36993684

3685+
seq(data(randval), cond=enable_cond)
37003686
seq(randval(next_value), cond=enable_cond)
37013687

37023688

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