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pipe -> df
1 parent 131c637 commit 6b7d5d9

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-16
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+16
-16
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veriloggen/lib/dataflow.py

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -309,9 +309,9 @@ def __str__(self):
309309
class _DataflowNumeric(vtypes._Numeric): pass
310310

311311
class _DataflowVariable(_DataflowNumeric):
312-
def __init__(self, pipe, stage_id, data, valid=None, ready=None,
312+
def __init__(self, df, stage_id, data, valid=None, ready=None,
313313
src_data=None, ops=None, resetcond=None, initval=None):
314-
self.pipe = pipe
314+
self.df = df
315315
self.stage_id = stage_id
316316
self.data = data
317317
self.valid = valid
@@ -325,7 +325,7 @@ def __init__(self, pipe, stage_id, data, valid=None, ready=None,
325325
self.preg_dict = {}
326326
if self.ready is not None:
327327
ready = vtypes.Int(1)
328-
self.pipe.m.Assign( self.ready(ready) )
328+
self.df.m.Assign( self.ready(ready) )
329329

330330
def prev(self, index, initval=0):
331331
if index == 0:
@@ -344,10 +344,10 @@ def prev(self, index, initval=0):
344344
p = self.prev_dict[i+1]
345345
continue
346346

347-
tmp_data, tmp_valid, tmp_ready = self.pipe._make_prev(p.data, p.valid, p.ready,
348-
self.valid, width, initval)
349-
p = _DataflowVariable(self.pipe, p.stage_id, tmp_data, tmp_valid, tmp_ready, p)
350-
self.pipe.vars.append(p)
347+
tmp_data, tmp_valid, tmp_ready = self.df._make_prev(p.data, p.valid, p.ready,
348+
self.valid, width, initval)
349+
p = _DataflowVariable(self.df, p.stage_id, tmp_data, tmp_valid, tmp_ready, p)
350+
self.df.vars.append(p)
351351
self.prev_dict[i+1] = p
352352

353353
return p
@@ -357,28 +357,28 @@ def output(self, data, valid=None, ready=None, nobuf=False):
357357
if nobuf:
358358
ovar = self
359359
else:
360-
ovar = self.pipe.stage(self, preg=self)
360+
ovar = self.df.stage(self, preg=self)
361361

362362
if not isinstance(data, (vtypes.Wire, vtypes.Output)):
363363
raise TypeError('Data signal must be Wire, not %s' % str(type(data)))
364364
else:
365-
ovar.pipe.m.Assign( data(ovar.data) )
365+
ovar.df.m.Assign( data(ovar.data) )
366366

367367
my_valid = vtypes.Int(1) if ovar.valid is None else ovar.valid
368368
if valid is None:
369369
pass
370370
elif not isinstance(valid, (vtypes.Wire, vtypes.Output)):
371371
raise TypeError('Valid signal must be Wire, not %s' % str(type(valid)))
372372
else:
373-
ovar.pipe.m.Assign( valid(my_valid) )
373+
ovar.df.m.Assign( valid(my_valid) )
374374

375375
if not ready:
376376
ready = vtypes.Int(1)
377377

378378
if ovar.ready is not None:
379379
prev_subst = ovar.ready.get_subst()
380380
if len(prev_subst) == 0:
381-
ovar.pipe.m.Assign( ovar.ready(ready) )
381+
ovar.df.m.Assign( ovar.ready(ready) )
382382
elif isinstance(prev_subst[0].right, vtypes.Int) and (prev_subst[0].right.value==1):
383383
ovar.ready.subst[0].overwrite_right( ready )
384384
else:
@@ -389,9 +389,9 @@ def output(self, data, valid=None, ready=None, nobuf=False):
389389
def reset(self, cond, initval=0):
390390
self.resetcond = cond
391391
self.initval = initval
392-
self.pipe.seq.add( self.data(initval), cond=cond )
392+
self.df.seq.add( self.data(initval), cond=cond )
393393
if self.valid is not None:
394-
self.pipe.seq.add( self.valid(0), cond=cond )
394+
self.df.seq.add( self.valid(0), cond=cond )
395395

396396
def bit_length(self):
397397
return self.data.bit_length()
@@ -471,8 +471,8 @@ def visit_float(self, node):
471471

472472
#-------------------------------------------------------------------------------
473473
class DataVisitor(_DataflowVisitor):
474-
def __init__(self, pipe):
475-
self.pipe = pipe
474+
def __init__(self, df):
475+
self.df = df
476476

477477
def pack_valid(self, lvalid, rvalid):
478478
if rvalid is not None and lvalid is not None:
@@ -518,7 +518,7 @@ def pack(self, *args):
518518
p = arg
519519
for i in range(diff):
520520
width = rslt[1].bit_length()
521-
p = self.pipe.stage(p, width=width, preg=arg)
521+
p = self.df.stage(p, width=width, preg=arg)
522522

523523
new_args.append(p)
524524

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