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dataflow.Counter with enable
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4 files changed

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‎tests/extension/dataflow_/counter_enable/Makefile‎

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TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
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ARGS=
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PYTHON=python3
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#PYTHON=python
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#OPT=-m pdb
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#OPT=-m cProfile -s time
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#OPT=-m cProfile -o profile.rslt
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.PHONY: all
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all: test
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.PHONY: run
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run:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS)
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.PHONY: test
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test:
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$(PYTHON) -m pytest -vv
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.PHONY: check
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check:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
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iverilog -tnull -Wall tmp.v
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rm -f tmp.v
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.PHONY: clean
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clean:
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rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

‎tests/extension/dataflow_/counter_enable/dataflow_counter_enable.py‎

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from __future__ import absolute_import
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from __future__ import print_function
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import sys
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import os
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import math
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# the next line can be removed after installation
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sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
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os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
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from veriloggen import *
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import veriloggen.dataflow as dataflow
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def mkMain(n=128, datawidth=32, numports=2):
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m = Module('main')
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clk = m.Input('CLK')
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rst = m.Input('RST')
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df = dataflow.DataflowManager(m, clk, rst)
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a = df.Counter(1, initval=0, maxval=8)
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b = df.Counter(1, initval=0, enable=(a == 0))
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c = df.Counter(1, initval=0, enable=df.Or(a == 0, a == 4))
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b.output('bdata', 'bvalid', 'bready')
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c.output('cdata', 'cvalid', 'cready')
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ready = 1
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bdata, bvalid = b.read(ready)
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cdata, cvalid = c.read(ready)
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seq = Seq(m, 'seq', clk, rst)
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seq.If(bvalid)(
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Systask('display', 'b=%d', bdata)
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)
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seq.If(cvalid)(
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Systask('display', 'c=%d', cdata)
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)
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return m
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def mkTest():
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m = Module('test')
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# target instance
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main = mkMain()
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# copy paras and ports
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params = m.copy_params(main)
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ports = m.copy_sim_ports(main)
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clk = ports['CLK']
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rst = ports['RST']
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uut = m.Instance(main, 'uut',
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params=m.connect_params(main),
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ports=m.connect_ports(main))
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simulation.setup_waveform(m, uut, m.get_vars())
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simulation.setup_clock(m, clk, hperiod=5)
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init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
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init.add(
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Delay(1000 * 100),
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Systask('finish'),
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)
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return m
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if __name__ == '__main__':
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test = mkTest()
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verilog = test.to_verilog('tmp.v')
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print(verilog)
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sim = simulation.Simulator(test)
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rslt = sim.run()
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print(rslt)
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# sim.view_waveform()

‎tests/extension/dataflow_/counter_enable/test_dataflow_counter_enable.py‎

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from __future__ import absolute_import
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from __future__ import print_function
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import veriloggen
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import dataflow_counter_enable
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expected_verilog = """
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module test;
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reg CLK;
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reg RST;
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main
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uut
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(
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.CLK(CLK),
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.RST(RST)
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);
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initial begin
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$dumpfile("uut.vcd");
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$dumpvars(0, uut, CLK, RST);
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end
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initial begin
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CLK = 0;
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forever begin
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#5 CLK = !CLK;
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end
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end
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initial begin
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RST = 0;
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#100;
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RST = 1;
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#100;
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RST = 0;
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#100000;
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$finish;
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end
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endmodule
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module main
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(
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input CLK,
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input RST
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);
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wire [32-1:0] bdata;
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wire bvalid;
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wire bready;
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assign bready = 1;
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wire [32-1:0] cdata;
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wire cvalid;
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wire cready;
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assign cready = 1;
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reg [32-1:0] _tmp_data_0;
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reg _tmp_valid_0;
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wire _tmp_ready_0;
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assign _tmp_ready_0 = (_tmp_ready_1 || !_tmp_valid_1) && _tmp_valid_0 && ((_tmp_ready_2 || !_tmp_valid_2) && _tmp_valid_0) && ((_tmp_ready_3 || !_tmp_valid_3) && _tmp_valid_0);
67+
reg [1-1:0] _tmp_data_1;
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reg _tmp_valid_1;
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wire _tmp_ready_1;
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assign _tmp_ready_1 = (_tmp_ready_4 || !_tmp_valid_4) && _tmp_valid_1;
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reg [1-1:0] _tmp_data_2;
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reg _tmp_valid_2;
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wire _tmp_ready_2;
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assign _tmp_ready_2 = (_tmp_ready_5 || !_tmp_valid_5) && (_tmp_valid_2 && _tmp_valid_3);
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reg [1-1:0] _tmp_data_3;
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reg _tmp_valid_3;
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wire _tmp_ready_3;
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assign _tmp_ready_3 = (_tmp_ready_5 || !_tmp_valid_5) && (_tmp_valid_2 && _tmp_valid_3);
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reg [32-1:0] _tmp_data_4;
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reg _tmp_valid_4;
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wire _tmp_ready_4;
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assign _tmp_ready_4 = (_tmp_ready_7 || !_tmp_valid_7) && _tmp_valid_4;
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reg [1-1:0] _tmp_data_5;
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reg _tmp_valid_5;
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wire _tmp_ready_5;
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assign _tmp_ready_5 = (_tmp_ready_6 || !_tmp_valid_6) && _tmp_valid_5;
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reg [32-1:0] _tmp_data_6;
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reg _tmp_valid_6;
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wire _tmp_ready_6;
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reg [32-1:0] _tmp_data_7;
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reg _tmp_valid_7;
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wire _tmp_ready_7;
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assign cdata = _tmp_data_6;
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assign cvalid = _tmp_valid_6;
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assign _tmp_ready_6 = cready;
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assign bdata = _tmp_data_7;
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assign bvalid = _tmp_valid_7;
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assign _tmp_ready_7 = bready;
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always @(posedge CLK) begin
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if(RST) begin
102+
_tmp_data_0 <= 1'd0;
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_tmp_valid_0 <= 0;
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_tmp_data_1 <= 0;
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_tmp_valid_1 <= 0;
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_tmp_data_2 <= 0;
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_tmp_valid_2 <= 0;
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_tmp_data_3 <= 0;
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_tmp_valid_3 <= 0;
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_tmp_data_4 <= 1'd0;
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_tmp_valid_4 <= 0;
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_tmp_data_5 <= 0;
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_tmp_valid_5 <= 0;
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_tmp_data_6 <= 1'd0;
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_tmp_valid_6 <= 0;
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_tmp_data_7 <= 0;
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_tmp_valid_7 <= 0;
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end else begin
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if((_tmp_ready_0 || !_tmp_valid_0) && 1 && 1) begin
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_tmp_data_0 <= (_tmp_data_0 >= 7)? 0 : _tmp_data_0 + 2'd1;
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end
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if(_tmp_valid_0 && _tmp_ready_0) begin
123+
_tmp_valid_0 <= 0;
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end
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if((_tmp_ready_0 || !_tmp_valid_0) && 1) begin
126+
_tmp_valid_0 <= 1;
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end
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if((_tmp_ready_1 || !_tmp_valid_1) && _tmp_ready_0 && _tmp_valid_0) begin
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_tmp_data_1 <= _tmp_data_0 == 1'd0;
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end
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if(_tmp_valid_1 && _tmp_ready_1) begin
132+
_tmp_valid_1 <= 0;
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end
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if((_tmp_ready_1 || !_tmp_valid_1) && _tmp_ready_0) begin
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_tmp_valid_1 <= _tmp_valid_0;
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end
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if((_tmp_ready_2 || !_tmp_valid_2) && _tmp_ready_0 && _tmp_valid_0) begin
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_tmp_data_2 <= _tmp_data_0 == 1'd0;
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end
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if(_tmp_valid_2 && _tmp_ready_2) begin
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_tmp_valid_2 <= 0;
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end
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if((_tmp_ready_2 || !_tmp_valid_2) && _tmp_ready_0) begin
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_tmp_valid_2 <= _tmp_valid_0;
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end
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if((_tmp_ready_3 || !_tmp_valid_3) && _tmp_ready_0 && _tmp_valid_0) begin
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_tmp_data_3 <= _tmp_data_0 == 4'd4;
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end
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if(_tmp_valid_3 && _tmp_ready_3) begin
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_tmp_valid_3 <= 0;
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end
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if((_tmp_ready_3 || !_tmp_valid_3) && _tmp_ready_0) begin
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_tmp_valid_3 <= _tmp_valid_0;
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end
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if((_tmp_ready_4 || !_tmp_valid_4) && _tmp_ready_1 && _tmp_valid_1 && _tmp_data_1) begin
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_tmp_data_4 <= _tmp_data_4 + 2'd1;
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end
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if(_tmp_valid_4 && _tmp_ready_4) begin
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_tmp_valid_4 <= 0;
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end
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if((_tmp_ready_4 || !_tmp_valid_4) && _tmp_ready_1) begin
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_tmp_valid_4 <= _tmp_valid_1;
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end
164+
if((_tmp_ready_5 || !_tmp_valid_5) && (_tmp_ready_2 && _tmp_ready_3) && (_tmp_valid_2 && _tmp_valid_3)) begin
165+
_tmp_data_5 <= _tmp_data_2 | _tmp_data_3;
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end
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if(_tmp_valid_5 && _tmp_ready_5) begin
168+
_tmp_valid_5 <= 0;
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end
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if((_tmp_ready_5 || !_tmp_valid_5) && (_tmp_ready_2 && _tmp_ready_3)) begin
171+
_tmp_valid_5 <= _tmp_valid_2 && _tmp_valid_3;
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end
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if((_tmp_ready_6 || !_tmp_valid_6) && _tmp_ready_5 && _tmp_valid_5 && _tmp_data_5) begin
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_tmp_data_6 <= _tmp_data_6 + 2'd1;
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end
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if(_tmp_valid_6 && _tmp_ready_6) begin
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_tmp_valid_6 <= 0;
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end
179+
if((_tmp_ready_6 || !_tmp_valid_6) && _tmp_ready_5) begin
180+
_tmp_valid_6 <= _tmp_valid_5;
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end
182+
if((_tmp_ready_7 || !_tmp_valid_7) && _tmp_ready_4 && _tmp_valid_4) begin
183+
_tmp_data_7 <= _tmp_data_4;
184+
end
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if(_tmp_valid_7 && _tmp_ready_7) begin
186+
_tmp_valid_7 <= 0;
187+
end
188+
if((_tmp_ready_7 || !_tmp_valid_7) && _tmp_ready_4) begin
189+
_tmp_valid_7 <= _tmp_valid_4;
190+
end
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end
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end
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always @(posedge CLK) begin
196+
if(bvalid && 1) begin
197+
$display("b=%d", bdata);
198+
end
199+
if(cvalid && 1) begin
200+
$display("c=%d", cdata);
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end
202+
end
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endmodule
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"""
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def test():
209+
veriloggen.reset()
210+
test_module = dataflow_counter_enable.mkTest()
211+
code = test_module.to_verilog()
212+
213+
from pyverilog.vparser.parser import VerilogParser
214+
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
215+
parser = VerilogParser()
216+
expected_ast = parser.parse(expected_verilog)
217+
codegen = ASTCodeGenerator()
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expected_code = codegen.visit(expected_ast)
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220+
assert(expected_code == code)

‎veriloggen/dataflow/dtypes.py‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2467,7 +2467,7 @@ def _set_attributes(self):
24672467

24682468

24692469
#-------------------------------------------------------------------------
2470-
def Counter(step=None, maxval=None, initval=0, reset=None, width=32, signed=False):
2470+
def Counter(step=None, maxval=None, initval=0, enable=None, reset=None, width=32, signed=False):
24712471
if step is None:
24722472
step = 1
24732473

@@ -2483,7 +2483,8 @@ def Counter(step=None, maxval=None, initval=0, reset=None, width=32, signed=Fals
24832483

24842484
if maxval is None:
24852485
return Icustom(lambda a, b: a + b,
2486-
step, initval=initval, reset=reset, width=width, signed=signed,
2486+
step, initval=initval, enable=enable, reset=reset,
2487+
width=width, signed=signed,
24872488
label='Counter')
24882489

24892490
maxval = _to_constant(maxval)
@@ -2492,7 +2493,8 @@ def Counter(step=None, maxval=None, initval=0, reset=None, width=32, signed=Fals
24922493
raw_maxval = maxval.value
24932494

24942495
return Icustom(lambda a, b: vtypes.Mux(a >= raw_maxval - raw_step, raw_initval, a + b),
2495-
step, initval=initval, reset=reset, width=width, signed=signed,
2496+
step, initval=initval, enable=enable, reset=reset,
2497+
width=width, signed=signed,
24962498
label='Counter')
24972499

24982500

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