MulAdd operator

shtaxxx · shtaxxx · commit 6543df3c188d · 2018-08-06T22:14:09.000+09:00
diff --git a/tests/extension/thread_/stream_muladd/Makefile b/tests/extension/thread_/stream_muladd/Makefile
@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd
diff --git a/tests/extension/thread_/stream_muladd/test_thread_stream_muladd.py b/tests/extension/thread_/stream_muladd/test_thread_stream_muladd.py
@@ -0,0 +1,18 @@
+from __future__ import absolute_import
+from __future__ import print_function
+
+import os
+import veriloggen
+import thread_stream_muladd
+
+
+def test(request):
+    veriloggen.reset()
+
+    simtype = request.config.getoption('--sim')
+
+    rslt = thread_stream_muladd.run(filename=None, simtype=simtype,
+                                    outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
+
+    verify_rslt = rslt.splitlines()[-1]
+    assert(verify_rslt == '# verify: PASSED')
diff --git a/tests/extension/thread_/stream_muladd/thread_stream_muladd.py b/tests/extension/thread_/stream_muladd/thread_stream_muladd.py
@@ -0,0 +1,140 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+import veriloggen.thread as vthread
+import veriloggen.types.axi as axi
+
+
+def mkLed():
+    m = Module('blinkled')
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+
+    datawidth = 32
+    addrwidth = 10
+    myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth)
+    ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth)
+    ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth)
+    ram_c = vthread.RAM(m, 'ram_c', clk, rst, datawidth, addrwidth)
+
+    strm = vthread.Stream(m, 'mystream', clk, rst)
+    a = strm.source('a')
+    b = strm.source('b')
+    c = strm.MulAdd(a, b, b)
+    strm.sink(c, 'c')
+
+    def comp_stream(size, offset):
+        strm.set_source('a', ram_a, offset, size)
+        strm.set_source('b', ram_b, offset, size)
+        strm.set_sink('c', ram_c, offset, size)
+        strm.run()
+        strm.join()
+
+    def comp_sequential(size, offset):
+        sum = 0
+        for i in range(size):
+            a = ram_a.read(i + offset)
+            b = ram_b.read(i + offset)
+            sum = a * b + b
+            ram_c.write(i + offset, sum)
+
+    def check(size, offset_stream, offset_seq):
+        all_ok = True
+        for i in range(size):
+            st = ram_c.read(i + offset_stream)
+            sq = ram_c.read(i + offset_seq)
+            if vthread.verilog.NotEql(st, sq):
+                all_ok = False
+        if all_ok:
+            print('# verify: PASSED')
+        else:
+            print('# verify: FAILED')
+
+    def comp(size):
+        # stream
+        offset = 0
+        myaxi.dma_read(ram_a, offset, 0, size)
+        myaxi.dma_read(ram_b, offset, 512, size)
+        comp_stream(size, offset)
+        myaxi.dma_write(ram_c, offset, 1024, size)
+
+        # sequential
+        offset = size
+        myaxi.dma_read(ram_a, offset, 0, size)
+        myaxi.dma_read(ram_b, offset, 512, size)
+        comp_sequential(size, offset)
+        myaxi.dma_write(ram_c, offset, 1024 * 2, size)
+
+        # verification
+        check(size, 0, offset)
+
+        vthread.finish()
+
+    th = vthread.Thread(m, 'th_comp', clk, rst, comp)
+    fsm = th.start(32)
+
+    return m
+
+
+def mkTest(memimg_name=None):
+    m = Module('test')
+
+    # target instance
+    led = mkLed()
+
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+
+    clk = ports['CLK']
+    rst = ports['RST']
+
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name)
+    memory.connect(ports, 'myaxi')
+
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+
+    #simulation.setup_waveform(m, uut)
+    simulation.setup_clock(m, clk, hperiod=5)
+    init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
+
+    init.add(
+        Delay(1000000),
+        Systask('finish'),
+    )
+
+    return m
+
+
+def run(filename='tmp.v', simtype='iverilog', outputfile=None):
+
+    if outputfile is None:
+        outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
+
+    memimg_name = 'memimg_' + outputfile
+
+    test = mkTest(memimg_name=memimg_name)
+
+    if filename is not None:
+        test.to_verilog(filename)
+
+    sim = simulation.Simulator(test, sim=simtype)
+    rslt = sim.run(outputfile=outputfile)
+    lines = rslt.splitlines()
+    if simtype == 'verilator' and lines[-1].startswith('-'):
+        rslt = '\n'.join(lines[:-1])
+    return rslt
+
+
+if __name__ == '__main__':
+    rslt = run(filename='tmp.v')
+    print(rslt)
diff --git a/veriloggen/stream/stypes.py b/veriloggen/stream/stypes.py
@@ -11,6 +11,7 @@
 
 from . import mul
 from . import div
+from . import madd
 
 
 # Object ID counter for object sorting key
@@ -1624,6 +1625,109 @@ def _implement(self, m, seq, svalid=None, senable=None):
         m.Instance(inst, self.name('lut'), ports=ports)
 
 
+class MulAdd(_SpecialOperator):
+    latency = 6 + 1
+
+    def __init__(self, a, b, c):
+        _SpecialOperator.__init__(self, a, b, c)
+
+    @property
+    def a(self):
+        return self.args[0]
+
+    @a.setter
+    def a(self, a):
+        self.args[0] = a
+
+    @property
+    def b(self):
+        return self.args[1]
+
+    @b.setter
+    def b(self, b):
+        self.args[1] = b
+
+    @property
+    def c(self):
+        return self.args[2]
+
+    @c.setter
+    def c(self, c):
+        self.args[2] = c
+
+    def _set_attributes(self):
+        a_fp = self.a.get_point()
+        b_fp = self.b.get_point()
+        c_fp = self.c.get_point()
+        a = self.a.bit_length()
+        b = self.b.bit_length()
+        c = self.c.bit_length()
+        self.width = max(a, b, c)
+        self.point = a_fp + b_fp
+        self.signed = self.a.get_signed() and self.b.get_signed() and self.c.get_signed()
+
+    def _implement(self, m, seq, svalid=None, senable=None):
+        if self.latency <= 3:
+            raise ValueError("Latency of '*' operator must be greater than 3")
+
+        width = self.bit_length()
+        signed = self.get_signed()
+
+        apoint = self.a.get_point()
+        bpoint = self.b.get_point()
+        cpoint = self.c.get_point()
+        awidth = self.a.bit_length()
+        bwidth = self.b.bit_length()
+        cwidth = self.c.bit_length()
+        asigned = self.a.get_signed()
+        bsigned = self.b.get_signed()
+        csigned = self.c.get_signed()
+        adata = self.a.sig_data
+        bdata = self.b.sig_data
+        cdata = self.c.sig_data
+
+        if apoint + bpoint != cpoint:
+            raise ValueError('apoint + bpoint == cpoint')
+
+        odata = m.Wire(self.name('madd_odata'),
+                       max(awidth + bwidth, cwidth), signed=signed)
+        odata_reg = m.Reg(self.name('madd_odata_reg'),
+                          max(awidth + bwidth, cwidth), signed=signed, initval=0)
+
+        data = m.Wire(self.name('data'), width, signed=signed)
+        self.sig_data = data
+
+        seq(odata_reg(odata), cond=senable)
+
+        m.Assign(data(odata_reg))
+
+        depth = self.latency - 1
+
+        inst = madd.get_madd(awidth, bwidth, cwidth,
+                             asigned, bsigned, csigned, depth)
+        clk = m._clock
+
+        update = m.Wire(self.name('madd_update'))
+
+        if senable is not None:
+            m.Assign(update(senable))
+        else:
+            m.Assign(update(1))
+
+        ports = [('CLK', clk), ('update', update),
+                 ('a', adata), ('b', bdata), ('c', cdata), ('d', odata)]
+
+        m.Instance(inst, self.name('madd'), ports=ports)
+
+    def eval(self):
+        vars = [var.eval() for var in self.vars]
+        for var in vars:
+            if not isinstance(var, int):
+                return MulAdd(*vars)
+
+        return vars[0] * vars[1] + vars[2]
+
+
 class PlusN(_SpecialOperator):
     latency = 1
 
@@ -1638,6 +1742,16 @@ def func(*args):
 
         self.op = func
 
+    def eval(self):
+        vars = [var.eval() for var in self.vars]
+        for var in vars:
+            if not isinstance(var, int):
+                return PlusN(*vars)
+        ret = 0
+        for var in vars:
+            ret += var
+        return ret
+
 
 def AddN(*vars):
     return PlusN(*vars)
