Fix the test codes for the simultaneous read/write accesses on an AXI slave interface.

Author: shtaxxx

tests/extension/types_/axi_/slave_readwrite_lite_simultaneous/test_types_axi_slave_readwrite_lite_simultaneous.py

@@ -56,7 +56,7 @@
   assign _axi_bready = 1;
   assign _axi_arcache = 3;
   assign _axi_arprot = 0;
-  reg [32-1:0] outstanding_wreq_count_0;
+  reg [3-1:0] outstanding_wcount_0;
   wire [32-1:0] _tmp_1;
   assign _tmp_1 = _axi_awaddr;
 
@@ -217,7 +217,7 @@
     _axi_wvalid = 0;
     _axi_araddr = 0;
     _axi_arvalid = 0;
-    outstanding_wreq_count_0 = 0;
+    outstanding_wcount_0 = 0;
     read_fsm = read_fsm_init;
     rsum = 0;
     __axi_cond_0_1 = 0;
@@ -239,7 +239,7 @@
 
   always @(posedge CLK) begin
     if(RST) begin
-      outstanding_wreq_count_0 <= 0;
+      outstanding_wcount_0 <= 0;
       _axi_araddr <= 0;
       _axi_arvalid <= 0;
       __axi_cond_0_1 <= 0;
@@ -272,11 +272,11 @@
       if(__axi_cond_5_1) begin
         _axi_wvalid <= 0;
       end 
-      if(_axi_wvalid && _axi_wready && !(_axi_bvalid && _axi_bready)) begin
-        outstanding_wreq_count_0 <= outstanding_wreq_count_0 + 1;
+      if(_axi_wvalid && _axi_wready && !(_axi_bvalid && _axi_bready) && (outstanding_wcount_0 < 7)) begin
+        outstanding_wcount_0 <= outstanding_wcount_0 + 1;
       end 
-      if(!(_axi_wvalid && _axi_wready) && (_axi_bvalid && _axi_bready) && (outstanding_wreq_count_0 > 0)) begin
-        outstanding_wreq_count_0 <= outstanding_wreq_count_0 - 1;
+      if(!(_axi_wvalid && _axi_wready) && (_axi_bvalid && _axi_bready) && (outstanding_wcount_0 > 0)) begin
+        outstanding_wcount_0 <= outstanding_wcount_0 - 1;
       end 
       if((read_fsm == 0) && (_axi_arready || !_axi_arvalid)) begin
         _axi_araddr <= 1024;
@@ -302,7 +302,7 @@
       if(_axi_awvalid && !_axi_awready) begin
         _axi_awvalid <= _axi_awvalid;
       end 
-      if((write_fsm == 1) && (_axi_wready || !_axi_wvalid)) begin
+      if((write_fsm == 1) && ((outstanding_wcount_0 < 6) && (_axi_wready || !_axi_wvalid))) begin
         _axi_wdata <= wdata;
         _axi_wvalid <= 1;
         _axi_wstrb <= { 4{ 1'd1 } };
@@ -319,7 +319,7 @@
       if(_axi_awvalid && !_axi_awready) begin
         _axi_awvalid <= _axi_awvalid;
       end 
-      if((write_fsm == 3) && (_axi_wready || !_axi_wvalid)) begin
+      if((write_fsm == 3) && ((outstanding_wcount_0 < 6) && (_axi_wready || !_axi_wvalid))) begin
         _axi_wdata <= wdata;
         _axi_wvalid <= 1;
         _axi_wstrb <= { 4{ 1'd1 } };
@@ -406,7 +406,7 @@
           end 
         end
         write_fsm_1: begin
-          if(_axi_wready || !_axi_wvalid) begin
+          if((outstanding_wcount_0 < 6) && (_axi_wready || !_axi_wvalid)) begin
             write_fsm <= write_fsm_2;
           end 
         end
@@ -417,7 +417,7 @@
           end 
         end
         write_fsm_3: begin
-          if(_axi_wready || !_axi_wvalid) begin
+          if((outstanding_wcount_0 < 6) && (_axi_wready || !_axi_wvalid)) begin
             write_fsm <= write_fsm_4;
           end 
         end

tests/extension/types_/axi_/slave_readwrite_simultaneous/test_types_axi_slave_readwrite_simultaneous.py

@@ -94,7 +94,7 @@
   assign _axi_arprot = 0;
   assign _axi_arqos = 0;
   assign _axi_aruser = 0;
-  reg [32-1:0] outstanding_wreq_count_0;
+  reg [3-1:0] outstanding_wcount_0;
   wire [32-1:0] _tmp_1;
   assign _tmp_1 = _axi_awaddr;
 
@@ -370,7 +370,7 @@
     _axi_araddr = 0;
     _axi_arlen = 0;
     _axi_arvalid = 0;
-    outstanding_wreq_count_0 = 0;
+    outstanding_wcount_0 = 0;
     read_fsm = read_fsm_init;
     rsum = 0;
     counter_27 = 0;
@@ -398,7 +398,7 @@
 
   always @(posedge CLK) begin
     if(RST) begin
-      outstanding_wreq_count_0 <= 0;
+      outstanding_wcount_0 <= 0;
       _axi_araddr <= 0;
       _axi_arlen <= 0;
       _axi_arvalid <= 0;
@@ -444,11 +444,11 @@
         _axi_wlast <= 0;
         last_32 <= 0;
       end 
-      if(_axi_wlast && _axi_wvalid && _axi_wready && !(_axi_bvalid && _axi_bready)) begin
-        outstanding_wreq_count_0 <= outstanding_wreq_count_0 + 1;
+      if(_axi_wlast && _axi_wvalid && _axi_wready && !(_axi_bvalid && _axi_bready) && (outstanding_wcount_0 < 7)) begin
+        outstanding_wcount_0 <= outstanding_wcount_0 + 1;
       end 
-      if(!(_axi_wlast && _axi_wvalid && _axi_wready) && (_axi_bvalid && _axi_bready) && (outstanding_wreq_count_0 > 0)) begin
-        outstanding_wreq_count_0 <= outstanding_wreq_count_0 - 1;
+      if(!(_axi_wlast && _axi_wvalid && _axi_wready) && (_axi_bvalid && _axi_bready) && (outstanding_wcount_0 > 0)) begin
+        outstanding_wcount_0 <= outstanding_wcount_0 - 1;
       end 
       if((read_fsm == 0) && ((_axi_arready || !_axi_arvalid) && (counter_27 == 0))) begin
         _axi_araddr <= 1024;
@@ -489,14 +489,14 @@
       if(_axi_awvalid && !_axi_awready) begin
         _axi_awvalid <= _axi_awvalid;
       end 
-      if((write_fsm == 1) && ((counter_29 > 0) && (_axi_wready || !_axi_wvalid) && (counter_29 > 0))) begin
+      if((write_fsm == 1) && ((counter_29 > 0) && (outstanding_wcount_0 < 6) && (_axi_wready || !_axi_wvalid) && (counter_29 > 0))) begin
         _axi_wdata <= wdata;
         _axi_wvalid <= 1;
         _axi_wlast <= 0;
         _axi_wstrb <= { 4{ 1'd1 } };
         counter_29 <= counter_29 - 1;
       end 
-      if((write_fsm == 1) && ((counter_29 > 0) && (_axi_wready || !_axi_wvalid) && (counter_29 > 0)) && (counter_29 == 1)) begin
+      if((write_fsm == 1) && ((counter_29 > 0) && (outstanding_wcount_0 < 6) && (_axi_wready || !_axi_wvalid) && (counter_29 > 0)) && (counter_29 == 1)) begin
         _axi_wlast <= 1;
         last_30 <= 1;
       end 
@@ -519,14 +519,14 @@
       if(_axi_awvalid && !_axi_awready) begin
         _axi_awvalid <= _axi_awvalid;
       end 
-      if((write_fsm == 3) && ((counter_31 > 0) && (_axi_wready || !_axi_wvalid) && (counter_31 > 0))) begin
+      if((write_fsm == 3) && ((counter_31 > 0) && (outstanding_wcount_0 < 6) && (_axi_wready || !_axi_wvalid) && (counter_31 > 0))) begin
         _axi_wdata <= wdata;
         _axi_wvalid <= 1;
         _axi_wlast <= 0;
         _axi_wstrb <= { 4{ 1'd1 } };
         counter_31 <= counter_31 - 1;
       end 
-      if((write_fsm == 3) && ((counter_31 > 0) && (_axi_wready || !_axi_wvalid) && (counter_31 > 0)) && (counter_31 == 1)) begin
+      if((write_fsm == 3) && ((counter_31 > 0) && (outstanding_wcount_0 < 6) && (_axi_wready || !_axi_wvalid) && (counter_31 > 0)) && (counter_31 == 1)) begin
         _axi_wlast <= 1;
         last_32 <= 1;
       end 
@@ -603,7 +603,7 @@
           end 
         end
         write_fsm_1: begin
-          if((counter_29 > 0) && (_axi_wready || !_axi_wvalid)) begin
+          if((counter_29 > 0) && (outstanding_wcount_0 < 6) && (_axi_wready || !_axi_wvalid)) begin
             wdata <= wdata + 1;
           end 
           if(last_30) begin
@@ -616,7 +616,7 @@
           end 
         end
         write_fsm_3: begin
-          if((counter_31 > 0) && (_axi_wready || !_axi_wvalid)) begin
+          if((counter_31 > 0) && (outstanding_wcount_0 < 6) && (_axi_wready || !_axi_wvalid)) begin
             wdata <= wdata + 1;
           end 
           if(last_32) begin