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applyMethod() is implemented.
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-57
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7 files changed

+319
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‎tests/extension/thread_/fixed_const/Makefile‎

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TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
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ARGS=
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PYTHON=python3
5+
#PYTHON=python
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#OPT=-m pdb
7+
#OPT=-m cProfile -s time
8+
#OPT=-m cProfile -o profile.rslt
9+
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.PHONY: all
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all: test
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.PHONY: run
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run:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS)
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.PHONY: test
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test:
19+
$(PYTHON) -m pytest -vv
20+
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.PHONY: check
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check:
23+
$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
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iverilog -tnull -Wall tmp.v
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rm -f tmp.v
26+
27+
.PHONY: clean
28+
clean:
29+
rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

‎tests/extension/thread_/fixed_const/test_thread_fixed_const.py‎

Lines changed: 149 additions & 0 deletions
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from __future__ import absolute_import
2+
from __future__ import print_function
3+
import veriloggen
4+
import thread_fixed_const
5+
6+
expected_verilog = """
7+
module test;
8+
9+
reg CLK;
10+
reg RST;
11+
12+
blinkled
13+
uut
14+
(
15+
.CLK(CLK),
16+
.RST(RST)
17+
);
18+
19+
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initial begin
21+
$dumpfile("uut.vcd");
22+
$dumpvars(0, uut);
23+
end
24+
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initial begin
27+
CLK = 0;
28+
forever begin
29+
#5 CLK = !CLK;
30+
end
31+
end
32+
33+
34+
initial begin
35+
RST = 0;
36+
#100;
37+
RST = 1;
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#100;
39+
RST = 0;
40+
#10000;
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$finish;
42+
end
43+
44+
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endmodule
46+
47+
48+
49+
module blinkled
50+
(
51+
input CLK,
52+
input RST
53+
);
54+
55+
reg [8-1:0] LED;
56+
reg signed [8-1:0] count;
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reg [32-1:0] th_blink;
58+
localparam th_blink_init = 0;
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reg signed [32-1:0] _th_blink_times_0;
60+
reg signed [32-1:0] _th_blink_next_val_1;
61+
reg signed [32-1:0] _th_blink_i_2;
62+
63+
always @(posedge CLK) begin
64+
if(RST) begin
65+
count <= 0;
66+
end else begin
67+
count <= count + 'sd8;
68+
end
69+
end
70+
71+
localparam th_blink_1 = 1;
72+
localparam th_blink_2 = 2;
73+
localparam th_blink_3 = 3;
74+
localparam th_blink_4 = 4;
75+
localparam th_blink_5 = 5;
76+
localparam th_blink_6 = 6;
77+
localparam th_blink_7 = 7;
78+
localparam th_blink_8 = 8;
79+
localparam th_blink_9 = 9;
80+
81+
always @(posedge CLK) begin
82+
if(RST) begin
83+
th_blink <= th_blink_init;
84+
_th_blink_times_0 <= 0;
85+
LED <= 0;
86+
_th_blink_i_2 <= 0;
87+
end else begin
88+
case(th_blink)
89+
th_blink_init: begin
90+
_th_blink_times_0 <= 10;
91+
th_blink <= th_blink_1;
92+
end
93+
th_blink_1: begin
94+
LED <= 0;
95+
th_blink <= th_blink_2;
96+
end
97+
th_blink_2: begin
98+
_th_blink_next_val_1 <= 0;
99+
th_blink <= th_blink_3;
100+
end
101+
th_blink_3: begin
102+
_th_blink_i_2 <= 0;
103+
th_blink <= th_blink_4;
104+
end
105+
th_blink_4: begin
106+
if(_th_blink_i_2 < _th_blink_times_0) begin
107+
th_blink <= th_blink_5;
108+
end else begin
109+
th_blink <= th_blink_9;
110+
end
111+
end
112+
th_blink_5: begin
113+
_th_blink_next_val_1 <= _th_blink_next_val_1 + 256;
114+
th_blink <= th_blink_6;
115+
end
116+
th_blink_6: begin
117+
LED <= _th_blink_next_val_1 >> 8;
118+
th_blink <= th_blink_7;
119+
end
120+
th_blink_7: begin
121+
$display("led = %d", LED);
122+
th_blink <= th_blink_8;
123+
end
124+
th_blink_8: begin
125+
_th_blink_i_2 <= _th_blink_i_2 + 1;
126+
th_blink <= th_blink_4;
127+
end
128+
endcase
129+
end
130+
end
131+
132+
133+
endmodule
134+
"""
135+
136+
137+
def test():
138+
veriloggen.reset()
139+
test_module = thread_fixed_const.mkTest()
140+
code = test_module.to_verilog()
141+
142+
from pyverilog.vparser.parser import VerilogParser
143+
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
144+
parser = VerilogParser()
145+
expected_ast = parser.parse(expected_verilog)
146+
codegen = ASTCodeGenerator()
147+
expected_code = codegen.visit(expected_ast)
148+
149+
assert(expected_code == code)

‎tests/extension/thread_/fixed_const/thread_fixed_const.py‎

Lines changed: 77 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,77 @@
1+
from __future__ import absolute_import
2+
from __future__ import print_function
3+
import sys
4+
import os
5+
6+
# the next line can be removed after installation
7+
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
8+
os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
9+
10+
from veriloggen import *
11+
import veriloggen.thread as vthread
12+
import veriloggen.types.fixed as fx
13+
14+
15+
def mkLed():
16+
m = Module('blinkled')
17+
clk = m.Input('CLK')
18+
rst = m.Input('RST')
19+
led = m.Reg('LED', 8, initval=0)
20+
21+
count = fx.FixedReg(m, 'count', 8, point=3, initval=0)
22+
23+
seq = Seq(m, 'seq', clk, rst)
24+
seq(
25+
count.inc()
26+
)
27+
28+
def blink(times):
29+
led.value = 0
30+
next_val = FixedConst(0, 8)
31+
for i in range(times):
32+
next_val = next_val + 1
33+
led.value = next_val
34+
print("led = ", led)
35+
36+
th = vthread.Thread(m, 'th_blink', clk, rst, blink)
37+
fsm = th.start(10)
38+
39+
return m
40+
41+
42+
def mkTest():
43+
m = Module('test')
44+
45+
# target instance
46+
led = mkLed()
47+
48+
# copy paras and ports
49+
params = m.copy_params(led)
50+
ports = m.copy_sim_ports(led)
51+
52+
clk = ports['CLK']
53+
rst = ports['RST']
54+
55+
uut = m.Instance(led, 'uut',
56+
params=m.connect_params(led),
57+
ports=m.connect_ports(led))
58+
59+
simulation.setup_waveform(m, uut)
60+
simulation.setup_clock(m, clk, hperiod=5)
61+
init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
62+
63+
init.add(
64+
Delay(10000),
65+
Systask('finish'),
66+
)
67+
68+
return m
69+
70+
if __name__ == '__main__':
71+
test = mkTest()
72+
verilog = test.to_verilog('tmp.v')
73+
print(verilog)
74+
75+
sim = simulation.Simulator(test)
76+
rslt = sim.run()
77+
print(rslt)

‎veriloggen/thread/compiler.py‎

Lines changed: 34 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -68,11 +68,7 @@ def __init__(self, m, name, clk, rst, fsm,
6868
self.datawidth = datawidth
6969

7070
fixed_intrinsics = {
71-
#'FixedInput': fxi._intrinsic_FixedInput,
72-
#'FixedOutput': fxi._intrinsic_FixedOutput,
73-
#'FixedOutputReg': fxi._intrinsic_FixedOutputReg,
74-
'FixedReg': fxi._intrinsic_FixedReg,
75-
#'FixedWire': fxi._intrinsic_FixedWire,
71+
'FixedConst': fxi._intrinsic_FixedConst,
7672
'to_fixed': fxi._intrinsic_to_fixed,
7773
'fixed_to_int': fxi._intrinsic_fixed_to_int,
7874
'fixed_to_int_low': fxi._intrinsic_fixed_to_int_low,
@@ -159,16 +155,17 @@ def visit_AugAssign(self, node):
159155
left_name = self.visit(node.target)
160156
left = self.getVariable(left_name, store=True)
161157

162-
method = getMethodName(node.op)
163-
if method is not None:
158+
try:
159+
method = getMethodName(node.op)
164160
rslt = applyMethod(left, method, right)
165-
rslt = optimize(rslt)
166-
else:
161+
162+
except NotImplementedError:
167163
op = getVeriloggenOp(node.op)
168164
if op is None:
169165
raise TypeError("Unsupported BinOp: %s" % str(node.op))
170166
rslt = op(left, right)
171-
rslt = optimize(rslt)
167+
168+
rslt = optimize(rslt)
172169

173170
self.setBind(left, rslt)
174171
self.setFsm()
@@ -735,32 +732,33 @@ def visit_Str(self, node):
735732
def visit_UnaryOp(self, node):
736733
value = self.visit(node.operand)
737734

738-
method = getMethodName(node.op)
739-
if method is not None:
735+
try:
736+
method = getMethodName(node.op)
740737
rslt = applyMethod(value, method)
741-
return optimize(rslt)
738+
except NotImplementedError:
739+
op = getVeriloggenOp(node.op)
740+
rslt = op(value)
742741

743-
op = getVeriloggenOp(node.op)
744-
rslt = op(value)
745742
return optimize(rslt)
746743

747744
def visit_BoolOp(self, node):
748745
values = [self.visit(v) for v in node.values]
749746

750-
method = getMethodName(node.op)
751-
if method is not None:
752-
rslt = value[0]
747+
try:
748+
method = getMethodName(node.op)
749+
rslt = values[0]
753750
for v in values[1:]:
754751
rslt = applyMethod(rslt, method, v)
755-
return optimize(rslt)
756752

757-
op = getVeriloggenOp(node.op)
758-
if op is None:
759-
raise TypeError("Unsupported BinOp: %s" % str(node.op))
753+
except NotImplementedError:
754+
op = getVeriloggenOp(node.op)
755+
if op is None:
756+
raise TypeError("Unsupported BinOp: %s" % str(node.op))
757+
758+
rslt = values[0]
759+
for v in values[1:]:
760+
rslt = op(rslt, v)
760761

761-
rslt = value[0]
762-
for v in values[1:]:
763-
rslt = op(rslt, v)
764762
return optimize(rslt)
765763

766764
def visit_BinOp(self, node):
@@ -772,15 +770,15 @@ def visit_BinOp(self, node):
772770
raise TypeError("Can not generate a corresponding node")
773771
return self._string_operation_plus(left, right)
774772

775-
method = getMethodName(node.op)
776-
if method is not None:
773+
try:
774+
method = getMethodName(node.op)
777775
rslt = applyMethod(left, method, right)
778-
return optimize(rslt)
779776

780-
op = getVeriloggenOp(node.op)
781-
if op is None:
782-
raise TypeError("Unsupported BinOp: %s" % str(node.op))
783-
rslt = op(left, right)
777+
except NotImplementedError:
778+
op = getVeriloggenOp(node.op)
779+
if op is None:
780+
raise TypeError("Unsupported BinOp: %s" % str(node.op))
781+
rslt = op(left, right)
784782

785783
return optimize(rslt)
786784

@@ -798,15 +796,15 @@ def visit_Compare(self, node):
798796
rslts = []
799797
for i, (method, op) in enumerate(zip(methods, ops)):
800798
if i == 0:
801-
if method is not None:
799+
try:
802800
rslts.append(applyMethod(left, method, comparators[i]))
803-
else:
801+
except NotImplementedError:
804802
rslts.append(op(left, comparators[i]))
805803
else:
806-
if method is not None:
804+
try:
807805
rslts.append(
808806
applyMethod(comparators[i - 1], method, comparators[i]))
809-
else:
807+
except NotImplementedError:
810808
rslts.append(op(comparators[i - 1], comparators[i]))
811809

812810
if len(rslts) == 1:

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