SubstreamMultiCycle works! But it should be improved for reduction operators in SubstreamMultiCycle.

shtaxxx · shtaxxx · commit 5e15d3e631fa · 2020-12-25T19:10:27.000+09:00
diff --git a/tests/extension/thread_/stream_substream_multicycle/Makefile b/tests/extension/thread_/stream_substream_multicycle/Makefile
@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd
diff --git a/tests/extension/thread_/stream_substream_multicycle/test_thread_stream_substream_multicycle.py b/tests/extension/thread_/stream_substream_multicycle/test_thread_stream_substream_multicycle.py
@@ -0,0 +1,18 @@
+from __future__ import absolute_import
+from __future__ import print_function
+
+import os
+import veriloggen
+import thread_stream_substream_multicycle
+
+
+def test(request):
+    veriloggen.reset()
+
+    simtype = request.config.getoption('--sim')
+
+    rslt = thread_stream_substream_multicycle.run(filename=None, simtype=simtype,
+                                                  outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
+
+    verify_rslt = rslt.splitlines()[-1]
+    assert(verify_rslt == '# verify: PASSED')
diff --git a/tests/extension/thread_/stream_substream_multicycle/thread_stream_substream_multicycle.py b/tests/extension/thread_/stream_substream_multicycle/thread_stream_substream_multicycle.py
@@ -0,0 +1,198 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+import veriloggen.thread as vthread
+import veriloggen.types.axi as axi
+
+
+def mkLed():
+    m = Module('blinkled')
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+
+    datawidth = 32
+    addrwidth = 10
+    myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth)
+    ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth)
+    ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth)
+    ram_c = vthread.RAM(m, 'ram_c', clk, rst, datawidth, addrwidth)
+
+    mulstrm = vthread.Stream(m, 'mul_stream', clk, rst)
+    mulx = mulstrm.source('x')
+    muly = mulstrm.source('y')
+    mulz = mulx * muly
+    mulz = mulz + mulx + muly - mulx - muly
+    mulstrm.sink(mulz, 'z')
+
+    wrapstrm = vthread.Stream(m, 'wrap_stream', clk, rst)
+    a = wrapstrm.source('a')
+    b = wrapstrm.source('b')
+    a = a + 1
+    b = b + 1
+    sub = wrapstrm.substream_multicycle(mulstrm)
+    sub.to_source('x', a)
+    sub.to_source('y', b)
+    c = sub.from_sink('z')
+    c = c + 100
+    wrapstrm.sink(c, 'c')
+
+    all_ok = m.TmpReg(initval=0)
+
+    def comp_stream_mul(size, offset):
+        mulstrm.set_source('x', ram_a, offset, size)
+        mulstrm.set_source('y', ram_b, offset, size)
+        mulstrm.set_sink('z', ram_c, offset, size)
+        mulstrm.run()
+        mulstrm.join()
+
+    def comp_stream_wrap(size, offset):
+        wrapstrm.set_source('a', ram_a, offset, size)
+        wrapstrm.set_source('b', ram_b, offset, size)
+        wrapstrm.set_sink('c', ram_c, offset, size)
+        wrapstrm.run()
+        wrapstrm.join()
+
+    def comp_sequential_mul(size, offset):
+        sum = 0
+        for i in range(size):
+            a = ram_a.read(i + offset)
+            b = ram_b.read(i + offset)
+            sum = a * b
+            ram_c.write(i + offset, sum)
+
+    def comp_sequential_wrap(size, offset):
+        sum = 0
+        for i in range(size):
+            a = ram_a.read(i + offset) + 1
+            b = ram_b.read(i + offset) + 1
+            sum = a * b
+            sum += 100
+            ram_c.write(i + offset, sum)
+
+    def check(size, offset_stream, offset_seq):
+        for i in range(size):
+            st = ram_c.read(i + offset_stream)
+            sq = ram_c.read(i + offset_seq)
+            if vthread.verilog.NotEql(st, sq):
+                all_ok.value = False
+        if all_ok:
+            print('# verify: PASSED')
+        else:
+            print('# verify: FAILED')
+
+    def comp(size):
+        all_ok.value = True
+
+        # mul
+        # stream
+        offset = 0
+        myaxi.dma_read(ram_a, offset, 0, size)
+        myaxi.dma_read(ram_b, offset, 512, size)
+        comp_stream_mul(size, offset)
+        myaxi.dma_write(ram_c, offset, 1024, size)
+
+        # sequential
+        offset = size
+        myaxi.dma_read(ram_a, offset, 0, size)
+        myaxi.dma_read(ram_b, offset, 512, size)
+        comp_sequential_mul(size, offset)
+        myaxi.dma_write(ram_c, offset, 1024 * 2, size)
+
+        # verification
+        print('# MUL')
+        myaxi.dma_read(ram_c, 0, 1024, size)
+        myaxi.dma_read(ram_c, offset, 1024 * 2, size)
+        check(size, 0, offset)
+
+        # wrap
+        # stream
+        offset = 0
+        myaxi.dma_read(ram_a, offset, 0, size)
+        myaxi.dma_read(ram_b, offset, 512, size)
+        comp_stream_wrap(size, offset)
+        myaxi.dma_write(ram_c, offset, 1024, size)
+
+        # sequential
+        offset = size
+        myaxi.dma_read(ram_a, offset, 0, size)
+        myaxi.dma_read(ram_b, offset, 512, size)
+        comp_sequential_wrap(size, offset)
+        myaxi.dma_write(ram_c, offset, 1024 * 2, size)
+
+        # verification
+        print('# WRAP')
+        myaxi.dma_read(ram_c, 0, 1024, size)
+        myaxi.dma_read(ram_c, offset, 1024 * 2, size)
+        check(size, 0, offset)
+
+        vthread.finish()
+
+    th = vthread.Thread(m, 'th_comp', clk, rst, comp)
+    # fsm = th.start(32)
+    fsm = th.start(8)
+
+    return m
+
+
+def mkTest(memimg_name=None):
+    m = Module('test')
+
+    # target instance
+    led = mkLed()
+
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+
+    clk = ports['CLK']
+    rst = ports['RST']
+
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name)
+    memory.connect(ports, 'myaxi')
+
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+
+    # simulation.setup_waveform(m, uut)
+    simulation.setup_clock(m, clk, hperiod=5)
+    init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
+
+    init.add(
+        Delay(1000000),
+        Systask('finish'),
+    )
+
+    return m
+
+
+def run(filename='tmp.v', simtype='iverilog', outputfile=None):
+
+    if outputfile is None:
+        outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
+
+    memimg_name = 'memimg_' + outputfile
+
+    test = mkTest(memimg_name=memimg_name)
+
+    if filename is not None:
+        test.to_verilog(filename)
+
+    sim = simulation.Simulator(test, sim=simtype)
+    rslt = sim.run(outputfile=outputfile)
+    lines = rslt.splitlines()
+    if simtype == 'verilator' and lines[-1].startswith('-'):
+        rslt = '\n'.join(lines[:-1])
+    return rslt
+
+
+if __name__ == '__main__':
+    rslt = run(filename='tmp.v')
+    print(rslt)
diff --git a/veriloggen/thread/stream.py b/veriloggen/thread/stream.py
@@ -404,7 +404,7 @@ def parameter(self, name=None, datawidth=None, point=0, signed=True):
         self.var_name_id_map[name] = _id
 
         var.next_parameter_data = self.module.Reg('_%s_next_parameter_data' % prefix,
-                                                 datawidth, initval=0)
+                                                  datawidth, initval=0)
         var.next_parameter_data.no_write_check = True
         var.has_parameter_data = False
 
@@ -425,6 +425,21 @@ def substream(self, substrm):
         self.substreams.append(sub)
         return sub
 
+    def substream_multicycle(self, substrm):
+        _id = self.var_id_count
+        name = 'substream_multicycle_%d' % _id
+
+        if name in self.var_name_map:
+            raise ValueError("'%s' is already defined in stream '%s'" %
+                             (name, self.name))
+
+        prefix = self._prefix(name)
+        self.var_id_count += 1
+
+        sub = SubstreamMultiCycle(self.module, self.clock, self.reset, substrm, self)
+        self.substreams.append(sub)
+        return sub
+
     def read_RAM(self, name, addr, when=None,
                  datawidth=None, point=0, signed=True):
 
@@ -1386,8 +1401,6 @@ def _synthesize_run(self):
                 self.dump_enable(1)
             )
 
-        self.fsm.If(start_cond, self.stream_oready).goto_next()
-
         substreams = self._collect_substreams()
         for sub in substreams:
             start_stage = sub.start_stage
@@ -1420,9 +1433,20 @@ def _synthesize_run(self):
                     cond(1)
                 )
 
+        self.fsm.If(start_cond, self.stream_oready).goto_next()
+
         # compute (at this cycle, source_idle <- 0)
         self.fsm.If(self.stream_oready).goto_next()
 
+# NOT OK
+#        substreams = self._collect_substreams()
+#        for sub in substreams:
+#            if isinstance(sub, SubstreamMultiCycle):
+#                sub_fsm = sub.substrm.fsm
+#                sub_fsm.seq.If(self.fsm.here)(
+#                    sub.substrm.stream_ivalid(sub.ii_count == 0)
+#                )
+
         # compute and join
         done_cond = None
         for key, source_idle in sorted(self.source_idle_map.items(),
@@ -3200,21 +3224,21 @@ def func(*args, **kwargs):
 
 class Substream(BaseSubstream):
 
-    def __init__(self, module, clock, reset, substrm, strm=None):
+    def __init__(self, module, clock, reset, substrm, strm):
         self.module = module
         self.clock = clock
         self.reset = reset
         self.reset_delay = 0
 
-        if strm is not None:
-            util.add_enable_cond(substrm.is_root, strm.busy, 0)
-            # parent to child
-            util.add_disable_cond(substrm.stream_oready, strm.busy, strm.stream_oready)
-            # child to parent
-            util.add_disable_cond(strm.stream_internal_oready, strm.busy, substrm.stream_internal_oready)
-
         BaseSubstream.__init__(self, substrm, strm)
 
+        util.add_enable_cond(substrm.is_root, strm.busy, 0)
+        # parent to child
+        util.add_disable_cond(substrm.stream_oready, strm.busy, strm.stream_oready)
+        # child to parent
+        util.add_disable_cond(strm.stream_internal_oready, strm.busy,
+                              substrm.stream_internal_oready)
+
     def to_source(self, name, data):
         source_name = self.substrm._dataname(name)
         cond = self.module.Reg(compiler._tmp_name(self.name('%s_cond' % source_name)),
@@ -3239,3 +3263,46 @@ def _collect_substreams(self):
         for s in ret:
             s.reset_delay += 1 + self.start_stage
         return ret
+
+
+class SubstreamMultiCycle(Substream):
+
+    def __init__(self, module, clock, reset, substrm, strm):
+        self.module = module
+        self.clock = clock
+        self.reset = reset
+        self.reset_delay = 0
+
+        BaseSubstream.__init__(self, substrm, strm)
+
+        util.add_enable_cond(substrm.is_root, strm.busy, 0)
+
+        self.iteration_interval = self.latency - 1
+        self.latency = 1 + 1
+
+        enable_cond = vtypes.Ands(self.strm.busy, self.strm.stream_oready, substrm.stream_ivalid)
+
+        self.ii_count = self.module.Reg(self.name('ii_count'),
+                                   int(math.ceil(math.log(self.iteration_interval, 2))) + 1, initval=0)
+        self.ii_stall_cond = self.module.Wire(self.name('ii_stall_cond'))
+        self.ii_stall_cond.assign(self.ii_count > 0)
+        util.add_disable_cond(self.strm.stream_internal_oready, self.ii_stall_cond, vtypes.Int(0))
+
+        self.strm.seq.If(enable_cond)(
+            self.ii_count.inc()
+        )
+        self.strm.seq.If(self.ii_count > 0)(
+            self.ii_count.inc()
+        )
+        self.strm.seq.If(self.ii_count == self.iteration_interval - 1)(
+            self.ii_count(0)
+        )
+
+        # parent to child
+        child_oready = vtypes.Ors(self.strm.stream_oready,
+                                  vtypes.Ands(self.substrm.stream_internal_oready, self.ii_stall_cond))
+        util.add_disable_cond(self.substrm.stream_oready, self.strm.busy, child_oready)
+
+        # child to parent
+        parent_internal_oready = vtypes.Not(self.ii_stall_cond)
+        util.add_disable_cond(self.strm.stream_internal_oready, self.strm.busy, parent_internal_oready)
