dataflow_stencil is updated for the updated fixed library.

Author: shtaxxx

examples/dataflow_stencil/dataflow_stencil.py

@@ -6,31 +6,34 @@
 from functools import reduce
 
 # the next line can be removed after installation
-sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))
+sys.path.insert(0, os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.abspath(__file__)))))
 
 from veriloggen import *
 import veriloggen.dataflow as dataflow
 import veriloggen.types.ram as ram
 import veriloggen.types.fixed as fixed
 
+
 def stencil(coe, data):
-    data = map(lambda x,y: x*y, data, coe)
-    rslt = reduce(lambda x,y: x+y, data)
+    data = map(lambda x, y: x * y, data, coe)
+    rslt = reduce(lambda x, y: x + y, data)
     return rslt
-    
+
+
 def mkStencilPipeline2D(coe=None, size=3, width=32, point=16):
     # size-port stream inputs
-    iports = [ dataflow.Variable('idata%d'%i, valid='ivalid%d'%i,
-                                 width=width, point=point, signed=True)
-               for i in range(size) ]
+    iports = [dataflow.Variable('idata%d' % i, valid='ivalid%d' % i,
+                                width=width, point=point, signed=True)
+              for i in range(size)]
 
     if coe is None:
-        coe = [ [ dataflow.Constant(1.0/(1.0*size*size), point=point) for i in range(size) ]
-                for j in range(size) ]
-        
+        coe = [[dataflow.Constant(1.0 / (1.0 * size * size), point=point) for i in range(size)]
+               for j in range(size)]
+
     # source data
-    data = [ [ d.prev(j) for j in range(size) ] for d in iports ]
-    
+    data = [[d.prev(j) for j in range(size)] for d in iports]
+
     # from 2D list to 1D list
     data_list = []
     coe_list = []
@@ -40,19 +43,20 @@ def mkStencilPipeline2D(coe=None, size=3, width=32, point=16):
 
     # computation by calling standard method
     rslt = stencil(coe_list, data_list)
-    
+
     rslt.output('odata', valid='ovalid')
-    
+
     df = dataflow.Dataflow(rslt)
     m = df.to_module('stencil_pipeline_2d')
 
-    #try:
+    # try:
     #    df.draw_graph()
-    #except:
+    # except:
     #    print('Dataflow graph could not be generated.', file=sys.stderr)
 
     return m
 
+
 def mkStencil(n=16, size=3, datawidth=32, point=16, coe_test=False):
     m = Module('stencil')
 
@@ -63,23 +67,23 @@ def mkStencil(n=16, size=3, datawidth=32, point=16, coe_test=False):
 
     start = m.Input('start')
     busy = m.OutputReg('busy', initval=0)
-    
+
     done = m.TmpReg(initval=0)
 
     # external RAM I/F
-    ext_src_rams = [ ram.RAMSlaveInterface(m, 'ext_src_ram%d' % i,
-                                              datawidth=datawidth, addrwidth=addrwidth)
-                      for i in range(size) ]
+    ext_src_rams = [ram.RAMSlaveInterface(m, 'ext_src_ram%d' % i,
+                                          datawidth=datawidth, addrwidth=addrwidth)
+                    for i in range(size)]
     ext_dst_ram = ram.RAMSlaveInterface(m, 'ext_dst_ram',
                                            datawidth=datawidth, addrwidth=addrwidth)
-    
+
     # RAM
     addrwidth = int(math.log(n, 2)) * 2
-    
-    src_rams = [ ram.SyncRAMManager(m, 'src_ram%d' % i, clk, rst,
-                                    datawidth=datawidth, addrwidth=addrwidth, numports=2)
-                  for i in range(size) ]
-                            
+
+    src_rams = [ram.SyncRAMManager(m, 'src_ram%d' % i, clk, rst,
+                                   datawidth=datawidth, addrwidth=addrwidth, numports=2)
+                for i in range(size)]
+
     dst_ram = ram.SyncRAMManager(m, 'dst_ram', clk, rst,
                                  datawidth=datawidth, addrwidth=addrwidth, numports=2)
 
@@ -94,7 +98,6 @@ def mkStencil(n=16, size=3, datawidth=32, point=16, coe_test=False):
     read_count = m.Reg('read_count', 32, initval=0)
     read_addr = m.Reg('read_addr', 32, initval=0)
 
-
     read_fsm(
         read_addr(0),
         read_count(0),
@@ -111,7 +114,7 @@ def mkStencil(n=16, size=3, datawidth=32, point=16, coe_test=False):
         read_addr.inc(),
         read_count.inc()
     )
-        
+
     idata = []
     ivalid = []
     for i, src_ram in enumerate(src_rams):
@@ -135,33 +138,32 @@ def mkStencil(n=16, size=3, datawidth=32, point=16, coe_test=False):
 
     read_fsm.make_always()
 
-
     # instance
     odata = m.Wire('odata', datawidth)
     ovalid = m.Wire('ovalid')
-    
+
     ports = []
-    ports.append( ('CLK', clk) )
-    ports.append( ('RST', rst) )    
-    
+    ports.append(('CLK', clk))
+    ports.append(('RST', rst))
+
     for i, (d, v) in enumerate(zip(idata, ivalid)):
-        ports.append( ('idata%d' % i, d) )
-        ports.append( ('ivalid%d' % i, v) )
+        ports.append(('idata%d' % i, d))
+        ports.append(('ivalid%d' % i, v))
 
-    ports.append( ('odata', odata) )
-    ports.append( ('ovalid', ovalid) )
+    ports.append(('odata', odata))
+    ports.append(('ovalid', ovalid))
 
     coe = None
     if coe_test:
-        coe = [ [ dataflow.Constant(1, point=point) for i in range(size) ]
-                for j in range(size) ]
+        coe = [[dataflow.Constant(1, point=point) for i in range(size)]
+               for j in range(size)]
         point = 0
-        
+
     st = mkStencilPipeline2D(size=3, width=datawidth, point=point, coe=coe)
     m.Instance(st, 'inst_stencil', ports=ports)
 
-    skip_offset = int(math.floor(size/2))
-    
+    skip_offset = int(math.floor(size / 2))
+
     # write FSM
     write_fsm = FSM(m, 'write_fsm', clk, rst)
     write_count = m.Reg('write_count', 32, initval=0)
@@ -170,17 +172,17 @@ def mkStencil(n=16, size=3, datawidth=32, point=16, coe_test=False):
     write_fsm(
         done(0)
     )
-    
+
     write_fsm.If(Ands(ovalid, write_count > skip_offset))(
         write_addr.inc()
     )
-    
+
     dst_ram.write(0, write_addr, odata, write_fsm.then)
-    
+
     write_fsm.If(ovalid)(
         write_count.inc(),
     )
-    
+
     write_fsm.If(write_count == n)(
         write_count(0),
         write_addr(skip_offset),
@@ -192,10 +194,11 @@ def mkStencil(n=16, size=3, datawidth=32, point=16, coe_test=False):
 
     return m
 
+
 def mkTest(n=16, size=3, datawidth=32, point=16, coe_test=False):
     if coe_test:
         point = 0
-    
+
     m = Module('test')
 
     addrwidth = int(math.log(n, 2))
@@ -204,23 +207,22 @@ def mkTest(n=16, size=3, datawidth=32, point=16, coe_test=False):
 
     params = m.copy_params(main)
     ports = m.copy_sim_ports(main)
-    
+
     clk = ports['CLK']
     rst = ports['RST']
 
     start = ports['start']
     busy = ports['busy']
-    
+
     uut = m.Instance(main, 'uut',
                      params=m.connect_params(main),
                      ports=m.connect_ports(main))
 
     reset_done = m.Reg('reset_done', initval=0)
     reset_stmt = []
-    reset_stmt.append( reset_done(0) )
-    reset_stmt.append( start(0) )
+    reset_stmt.append(reset_done(0))
+    reset_stmt.append(start(0))
 
-    
     # src RAM
     for i in range(3):
         addr = ports['ext_src_ram%d_addr' % i]
@@ -239,7 +241,6 @@ def mkTest(n=16, size=3, datawidth=32, point=16, coe_test=False):
     reset_stmt.append(addr(2))
     reset_stmt.append(wdata(0))
     reset_stmt.append(wenable(0))
-    
 
     simulation.setup_waveform(m, uut)
     simulation.setup_clock(m, clk, hperiod=5)
@@ -256,12 +257,12 @@ def mkTest(n=16, size=3, datawidth=32, point=16, coe_test=False):
     )
 
     fsm = FSM(m, 'fsm', clk, rst)
-    
+
     fsm.goto_next(cond=reset_done)
 
     for i in range(3):
         addr = ports['ext_src_ram%d_addr' % i]
-        fsm.add( addr(-1) )
+        fsm.add(addr(-1))
 
     fsm.goto_next()
 
@@ -270,25 +271,26 @@ def mkTest(n=16, size=3, datawidth=32, point=16, coe_test=False):
         rdata = ports['ext_src_ram%d_rdata' % i]
         wdata = ports['ext_src_ram%d_wdata' % i]
         wenable = ports['ext_src_ram%d_wenable' % i]
-        next_addr = (addr+1) % (n*n)
-        fsm.add( addr.inc() )
-        fsm.add( wdata(fixed.FixedConst(90, point)) )
-        fsm.add( wenable(1) )
-        fsm.add( wenable(0), cond=AndList(wenable, addr==2**addrwidth-1) )
-
-    fsm.goto_next(cond=AndList(wenable, ports['ext_src_ram0_addr']==2**addrwidth-1))
-    
+        next_addr = (addr + 1) % (n * n)
+        fsm.add(addr.inc())
+        fsm.add(wdata(fixed.FixedConst(90, point).raw))
+        fsm.add(wenable(1))
+        fsm.add(wenable(0), cond=AndList(wenable, addr == 2**addrwidth - 1))
+
+    fsm.goto_next(cond=AndList(
+        wenable, ports['ext_src_ram0_addr'] == 2**addrwidth - 1))
+
     fsm.goto_next(cond=Not(busy))
-    
-    fsm.add( start(1) )
-    fsm.add( start(0), delay=1 )
+
+    fsm.add(start(1))
+    fsm.add(start(0), delay=1)
     fsm.goto_next()
-    
+
     fsm.goto_next(cond=busy)
 
     fsm.goto_next(cond=Not(busy))
 
-    fsm.add( Systask('finish') )
+    fsm.add(Systask('finish'))
 
     fsm.make_always()
 
@@ -299,7 +301,7 @@ def mkTest(n=16, size=3, datawidth=32, point=16, coe_test=False):
     #test = mkTest(n, coe_test=True)
     test = mkTest(n)
     verilog = test.to_verilog('tmp.v')
-    #print(verilog)
+    # print(verilog)
 
     # run simulator (Icarus Verilog)
     sim = simulation.Simulator(test)