Merge branch 'feature_axi_stream' into develop

Author: shtaxxx

examples/thread_stream_axi_stream_fifo/test_thread_stream_axi_stream_fifo.py

@@ -552,7 +552,8 @@
   assign mystream_reduce_sum_data = _reduceadd_data_5;
   wire [1-1:0] mystream_reduce_sum_valid_data;
   assign mystream_reduce_sum_valid_data = _pulse_data_7;
-  reg _set_flag_30;
+  wire _set_flag_30;
+  assign _set_flag_30 = th_comp == 25;
   assign fifo_a_deq = (_mystream_reduce_stream_oready && _mystream_reduce_a_source_fifo_deq && (_mystream_reduce_a_source_sel == 1) && !fifo_a_empty)? 1 : 0;
   localparam _tmp_31 = 1;
   wire [_tmp_31-1:0] _tmp_32;
@@ -563,10 +564,12 @@
   assign mystream_reduce_a_data = __variable_wdata_0;
   reg [32-1:0] _mystream_reduce_a_source_fsm_0;
   localparam _mystream_reduce_a_source_fsm_0_init = 0;
-  reg _set_flag_33;
+  wire _set_flag_33;
+  assign _set_flag_33 = th_comp == 26;
   reg signed [32-1:0] __variable_wdata_1;
   assign mystream_reduce_reduce_size_data = __variable_wdata_1;
-  reg _set_flag_34;
+  wire _set_flag_34;
+  assign _set_flag_34 = th_comp == 27;
   reg _tmp_35;
   reg _tmp_36;
   reg _tmp_37;
@@ -602,7 +605,8 @@
   reg signed [32-1:0] _plus_data_10;
   wire signed [32-1:0] mystream_bias_z_data;
   assign mystream_bias_z_data = _plus_data_10;
-  reg _set_flag_57;
+  wire _set_flag_57;
+  assign _set_flag_57 = th_comp == 28;
   assign fifo_b_deq = (_mystream_bias_stream_oready && _mystream_bias_x_source_fifo_deq && (_mystream_bias_x_source_sel == 1) && !fifo_b_empty)? 1 : 0;
   localparam _tmp_58 = 1;
   wire [_tmp_58-1:0] _tmp_59;
@@ -613,7 +617,8 @@
   assign mystream_bias_x_data = __variable_wdata_8;
   reg [32-1:0] _mystream_bias_x_source_fsm_0;
   localparam _mystream_bias_x_source_fsm_0_init = 0;
-  reg _set_flag_60;
+  wire _set_flag_60;
+  assign _set_flag_60 = th_comp == 29;
   assign ram_b_0_addr = (_mystream_bias_stream_oready && _mystream_bias_y_source_ram_renable && (_mystream_bias_y_source_sel == 2))? _mystream_bias_y_source_ram_raddr : 
                         (_tmp_16)? _tmp_14 : 0;
   assign ram_b_0_enable = (_mystream_bias_stream_oready && _mystream_bias_y_source_ram_renable && (_mystream_bias_y_source_sel == 2))? 1'd1 : 
@@ -627,7 +632,8 @@
   assign mystream_bias_y_data = __variable_wdata_9;
   reg [32-1:0] _mystream_bias_y_source_fsm_1;
   localparam _mystream_bias_y_source_fsm_1_init = 0;
-  reg _set_flag_63;
+  wire _set_flag_63;
+  assign _set_flag_63 = th_comp == 30;
   reg _tmp_64;
   reg _tmp_65;
   reg _tmp_66;
@@ -643,7 +649,8 @@
   assign _mystream_bias_stream_oready = ((_mystream_bias_sink_busy && (_mystream_bias_z_sink_sel == 3))? !fifo_c_almost_full : 1) && (((_mystream_bias_source_busy && (_mystream_bias_x_source_sel == 1))? !fifo_b_empty || _mystream_bias_x_idle : 1) && 1);
   reg [32-1:0] _mystream_bias_z_sink_fsm_2;
   localparam _mystream_bias_z_sink_fsm_2_init = 0;
-  reg _set_flag_72;
+  wire _set_flag_72;
+  assign _set_flag_72 = th_comp == 31;
   assign _mystream_reduce_run_flag = (_set_flag_72)? 1 : 0;
   reg _tmp_73;
   reg _tmp_74;
@@ -693,7 +700,8 @@
   assign _mystream_reduce_sink_busy = _tmp_113;
   reg __mystream_reduce_sink_busy_1;
   assign _mystream_reduce_busy = _mystream_reduce_source_busy || _mystream_reduce_sink_busy || _mystream_reduce_busy_buf;
-  reg _set_flag_114;
+  wire _set_flag_114;
+  assign _set_flag_114 = th_comp == 33;
   assign _mystream_bias_run_flag = (_set_flag_114)? 1 : 0;
   reg _tmp_115;
   reg _tmp_116;
@@ -1255,17 +1263,14 @@
       _pulse_data_7 <= 1'sd0;
       _pulse_count_7 <= 0;
       _pulse_prev_count_max_7 <= 0;
-      _set_flag_30 <= 0;
       _mystream_reduce_a_source_mode <= 4'b0;
       _mystream_reduce_a_source_size <= 0;
       _mystream_reduce_a_source_sel <= 0;
       _mystream_reduce_a_source_size_buf <= 0;
       __variable_wdata_0 <= 0;
       _mystream_reduce_a_source_count <= 0;
-      _set_flag_33 <= 0;
       _mystream_reduce_reduce_size_next_constant_data <= 0;
       __variable_wdata_1 <= 0;
-      _set_flag_34 <= 0;
       _tmp_35 <= 0;
       _tmp_36 <= 0;
       _tmp_37 <= 0;
@@ -1292,7 +1297,6 @@
       _mystream_reduce_sum_sink_size_buf <= 0;
       _mystream_reduce_sum_sink_count <= 0;
       _mystream_reduce_sum_sink_fifo_wdata <= 0;
-      _set_flag_72 <= 0;
       _tmp_73 <= 0;
       _tmp_74 <= 0;
       _tmp_75 <= 0;
@@ -1439,10 +1443,6 @@
       if(__mystream_reduce_stream_ivalid_7 && _mystream_reduce_stream_oready) begin
         _pulse_prev_count_max_7 <= _pulse_current_count_7 >= __delay_data_17__delay_16__delay_15__delay_14____variable_1 - 1;
       end 
-      _set_flag_30 <= 0;
-      if(th_comp == 25) begin
-        _set_flag_30 <= 1;
-      end 
       if(_set_flag_30) begin
         _mystream_reduce_a_source_mode <= 4'b1000;
         _mystream_reduce_a_source_size <= _th_comp_read_size_0;
@@ -1469,22 +1469,12 @@
         _mystream_reduce_a_source_fifo_deq <= 0;
         _mystream_reduce_a_idle <= 1;
       end 
-      _set_flag_33 <= 0;
-      if(th_comp == 26) begin
-        _set_flag_33 <= 1;
-      end 
       if(_set_flag_33) begin
         _mystream_reduce_reduce_size_next_constant_data <= _th_comp_reduce_size_2;
       end 
       if(_mystream_reduce_source_start) begin
         __variable_wdata_1 <= _mystream_reduce_reduce_size_next_constant_data;
       end 
-      if(_mystream_reduce_stream_oready) begin
-        _set_flag_34 <= 0;
-      end 
-      if(_mystream_reduce_stream_oready && (th_comp == 27)) begin
-        _set_flag_34 <= 1;
-      end 
       if(_mystream_reduce_stream_oready) begin
         _tmp_35 <= _set_flag_34;
       end 
@@ -1564,10 +1554,6 @@
         _mystream_reduce_sum_sink_fifo_enq <= 1;
         _mystream_reduce_sum_sink_count <= _mystream_reduce_sum_sink_count - 1;
       end 
-      _set_flag_72 <= 0;
-      if(th_comp == 31) begin
-        _set_flag_72 <= 1;
-      end 
       if(_mystream_reduce_stream_oready) begin
         _tmp_73 <= _mystream_reduce_source_start;
       end 
@@ -1745,9 +1731,15 @@
             _mystream_reduce_source_stop <= 1;
             _mystream_reduce_source_busy <= 0;
           end 
+          if(_mystream_reduce_stream_oready && (_mystream_reduce_a_idle && (_mystream_reduce_fsm == 3)) && _mystream_reduce_run_flag) begin
+            _mystream_reduce_source_start <= 1;
+          end 
           if(_mystream_reduce_stream_oready && (_mystream_reduce_a_idle && (_mystream_reduce_fsm == 3))) begin
             _mystream_reduce_fsm <= _mystream_reduce_fsm_init;
           end 
+          if(_mystream_reduce_stream_oready && (_mystream_reduce_a_idle && (_mystream_reduce_fsm == 3)) && _mystream_reduce_run_flag) begin
+            _mystream_reduce_fsm <= _mystream_reduce_fsm_1;
+          end 
         end
       endcase
     end
@@ -1766,14 +1758,12 @@
       _mystream_bias_z_sink_fifo_enq <= 0;
       __mystream_bias_stream_ivalid_1 <= 0;
       _plus_data_10 <= 0;
-      _set_flag_57 <= 0;
       _mystream_bias_x_source_mode <= 4'b0;
       _mystream_bias_x_source_size <= 0;
       _mystream_bias_x_source_sel <= 0;
       _mystream_bias_x_source_size_buf <= 0;
       __variable_wdata_8 <= 0;
       _mystream_bias_x_source_count <= 0;
-      _set_flag_60 <= 0;
       _mystream_bias_y_source_mode <= 4'b0;
       _mystream_bias_y_source_offset <= 0;
       _mystream_bias_y_source_size <= 0;
@@ -1785,7 +1775,6 @@
       __variable_wdata_9 <= 0;
       _mystream_bias_y_source_ram_raddr <= 0;
       _mystream_bias_y_source_count <= 0;
-      _set_flag_63 <= 0;
       _tmp_64 <= 0;
       _tmp_65 <= 0;
       _tmp_66 <= 0;
@@ -1798,7 +1787,6 @@
       _mystream_bias_z_sink_size_buf <= 0;
       _mystream_bias_z_sink_count <= 0;
       _mystream_bias_z_sink_fifo_wdata <= 0;
-      _set_flag_114 <= 0;
       _tmp_115 <= 0;
       _tmp_116 <= 0;
       _tmp_117 <= 0;
@@ -1833,10 +1821,6 @@
       if(_mystream_bias_stream_oready) begin
         _plus_data_10 <= mystream_bias_x_data + mystream_bias_y_data;
       end 
-      _set_flag_57 <= 0;
-      if(th_comp == 28) begin
-        _set_flag_57 <= 1;
-      end 
       if(_set_flag_57) begin
         _mystream_bias_x_source_mode <= 4'b1000;
         _mystream_bias_x_source_size <= _th_comp_write_size_1;
@@ -1863,10 +1847,6 @@
         _mystream_bias_x_source_fifo_deq <= 0;
         _mystream_bias_x_idle <= 1;
       end 
-      _set_flag_60 <= 0;
-      if(th_comp == 29) begin
-        _set_flag_60 <= 1;
-      end 
       if(_set_flag_60) begin
         _mystream_bias_y_source_mode <= 4'b1;
         _mystream_bias_y_source_offset <= 0;
@@ -1899,12 +1879,6 @@
         _mystream_bias_y_source_ram_renable <= 0;
         _mystream_bias_y_idle <= 1;
       end 
-      if(_mystream_bias_stream_oready) begin
-        _set_flag_63 <= 0;
-      end 
-      if(_mystream_bias_stream_oready && (th_comp == 30)) begin
-        _set_flag_63 <= 1;
-      end 
       if(_mystream_bias_stream_oready) begin
         _tmp_64 <= _set_flag_63;
       end 
@@ -1942,10 +1916,6 @@
         _mystream_bias_z_sink_fifo_enq <= 1;
         _mystream_bias_z_sink_count <= _mystream_bias_z_sink_count - 1;
       end 
-      _set_flag_114 <= 0;
-      if(th_comp == 33) begin
-        _set_flag_114 <= 1;
-      end 
       if(_mystream_bias_stream_oready) begin
         _tmp_115 <= _mystream_bias_source_start;
       end 
@@ -2038,9 +2008,15 @@
             _mystream_bias_source_stop <= 1;
             _mystream_bias_source_busy <= 0;
           end 
+          if(_mystream_bias_stream_oready && (_mystream_bias_x_idle && _mystream_bias_y_idle && (_mystream_bias_fsm == 3)) && _mystream_bias_run_flag) begin
+            _mystream_bias_source_start <= 1;
+          end 
           if(_mystream_bias_stream_oready && (_mystream_bias_x_idle && _mystream_bias_y_idle && (_mystream_bias_fsm == 3))) begin
             _mystream_bias_fsm <= _mystream_bias_fsm_init;
           end 
+          if(_mystream_bias_stream_oready && (_mystream_bias_x_idle && _mystream_bias_y_idle && (_mystream_bias_fsm == 3)) && _mystream_bias_run_flag) begin
+            _mystream_bias_fsm <= _mystream_bias_fsm_1;
+          end 
         end
       endcase
     end

tests/extension/thread_/stream_axi_stream/test_thread_stream_axi_stream.py

@@ -330,7 +330,8 @@
   reg signed [32-1:0] _plus_data_2;
   wire signed [32-1:0] mystream_c_data;
   assign mystream_c_data = _plus_data_2;
-  reg _set_flag_27;
+  wire _set_flag_27;
+  assign _set_flag_27 = th_comp == 17;
   assign ram_a_0_addr = (_mystream_stream_oready && _mystream_a_source_ram_renable && (_mystream_a_source_sel == 1))? _mystream_a_source_ram_raddr : 0;
   assign ram_a_0_enable = (_mystream_stream_oready && _mystream_a_source_ram_renable && (_mystream_a_source_sel == 1))? 1'd1 : 0;
   localparam _tmp_28 = 1;
@@ -342,7 +343,8 @@
   assign mystream_a_data = __variable_wdata_0;
   reg [32-1:0] _mystream_a_source_fsm_0;
   localparam _mystream_a_source_fsm_0_init = 0;
-  reg _set_flag_30;
+  wire _set_flag_30;
+  assign _set_flag_30 = th_comp == 18;
   assign ram_b_0_addr = (_mystream_stream_oready && _mystream_b_source_ram_renable && (_mystream_b_source_sel == 2))? _mystream_b_source_ram_raddr : 0;
   assign ram_b_0_enable = (_mystream_stream_oready && _mystream_b_source_ram_renable && (_mystream_b_source_sel == 2))? 1'd1 : 0;
   localparam _tmp_31 = 1;
@@ -354,7 +356,8 @@
   assign mystream_b_data = __variable_wdata_1;
   reg [32-1:0] _mystream_b_source_fsm_1;
   localparam _mystream_b_source_fsm_1_init = 0;
-  reg _set_flag_33;
+  wire _set_flag_33;
+  assign _set_flag_33 = th_comp == 19;
   reg _tmp_34;
   reg _tmp_35;
   reg _tmp_36;
@@ -370,7 +373,8 @@
   assign ram_c_0_enable = (_mystream_stream_oready && _mystream_c_sink_wenable && (_mystream_c_sink_sel == 3))? 1'd1 : 0;
   reg [32-1:0] _mystream_c_sink_fsm_2;
   localparam _mystream_c_sink_fsm_2_init = 0;
-  reg _set_flag_43;
+  wire _set_flag_43;
+  assign _set_flag_43 = th_comp == 20;
   assign _mystream_run_flag = (_set_flag_43)? 1 : 0;
   reg _tmp_44;
   reg _tmp_45;
@@ -853,7 +857,6 @@
       _mystream_c_sink_fifo_enq <= 0;
       __mystream_stream_ivalid_1 <= 0;
       _plus_data_2 <= 0;
-      _set_flag_27 <= 0;
       _mystream_a_source_mode <= 4'b0;
       _mystream_a_source_offset <= 0;
       _mystream_a_source_size <= 0;
@@ -865,7 +868,6 @@
       __variable_wdata_0 <= 0;
       _mystream_a_source_ram_raddr <= 0;
       _mystream_a_source_count <= 0;
-      _set_flag_30 <= 0;
       _mystream_b_source_mode <= 4'b0;
       _mystream_b_source_offset <= 0;
       _mystream_b_source_size <= 0;
@@ -877,7 +879,6 @@
       __variable_wdata_1 <= 0;
       _mystream_b_source_ram_raddr <= 0;
       _mystream_b_source_count <= 0;
-      _set_flag_33 <= 0;
       _tmp_34 <= 0;
       _tmp_35 <= 0;
       _tmp_36 <= 0;
@@ -898,7 +899,6 @@
       _mystream_c_sink_waddr <= 0;
       _mystream_c_sink_count <= 0;
       _mystream_c_sink_wdata <= 0;
-      _set_flag_43 <= 0;
       _tmp_44 <= 0;
       _tmp_45 <= 0;
       _tmp_46 <= 0;
@@ -933,10 +933,6 @@
       if(_mystream_stream_oready) begin
         _plus_data_2 <= mystream_a_data + mystream_b_data;
       end 
-      _set_flag_27 <= 0;
-      if(th_comp == 17) begin
-        _set_flag_27 <= 1;
-      end 
       if(_set_flag_27) begin
         _mystream_a_source_mode <= 4'b1;
         _mystream_a_source_offset <= _th_comp_offset_3;
@@ -969,10 +965,6 @@
         _mystream_a_source_ram_renable <= 0;
         _mystream_a_idle <= 1;
       end 
-      _set_flag_30 <= 0;
-      if(th_comp == 18) begin
-        _set_flag_30 <= 1;
-      end 
       if(_set_flag_30) begin
         _mystream_b_source_mode <= 4'b1;
         _mystream_b_source_offset <= _th_comp_offset_3;
@@ -1005,12 +997,6 @@
         _mystream_b_source_ram_renable <= 0;
         _mystream_b_idle <= 1;
       end 
-      if(_mystream_stream_oready) begin
-        _set_flag_33 <= 0;
-      end 
-      if(_mystream_stream_oready && (th_comp == 19)) begin
-        _set_flag_33 <= 1;
-      end 
       if(_mystream_stream_oready) begin
         _tmp_34 <= _set_flag_33;
       end 
@@ -1062,10 +1048,6 @@
         _mystream_c_sink_wenable <= 1;
         _mystream_c_sink_count <= _mystream_c_sink_count - 1;
       end 
-      _set_flag_43 <= 0;
-      if(th_comp == 20) begin
-        _set_flag_43 <= 1;
-      end 
       if(_mystream_stream_oready) begin
         _tmp_44 <= _mystream_source_start;
       end 
@@ -1158,9 +1140,15 @@
             _mystream_source_stop <= 1;
             _mystream_source_busy <= 0;
           end 
+          if(_mystream_stream_oready && (_mystream_a_idle && _mystream_b_idle && (_mystream_fsm == 3)) && _mystream_run_flag) begin
+            _mystream_source_start <= 1;
+          end 
           if(_mystream_stream_oready && (_mystream_a_idle && _mystream_b_idle && (_mystream_fsm == 3))) begin
             _mystream_fsm <= _mystream_fsm_init;
           end 
+          if(_mystream_stream_oready && (_mystream_a_idle && _mystream_b_idle && (_mystream_fsm == 3)) && _mystream_run_flag) begin
+            _mystream_fsm <= _mystream_fsm_1;
+          end 
         end
       endcase
     end