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Merge branch 'develop' into feature_axi_stream
2 parents 194fd86 + c7b8595 commit 4f918bc

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veriloggen/stream/stypes.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2562,8 +2562,8 @@ def _implement(self, m, seq, svalid=None, senable=None):
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value = (count >= (size_data - 1))
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reset_value = initval_data
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if self.size is not None:
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reset_value = initval_data
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for op in self.ops:
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if not isinstance(op, type):
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reset_value = op(reset_value, rdata)

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