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shtaxxxshtaxxx
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Merge branch 'fix_axi_lite' into develop
2 parents ad9fd93 + c7dc37b commit 4dfbb26

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16 files changed

+891
-451
lines changed

16 files changed

+891
-451
lines changed

‎examples/axi_stream_ultra96v2_pynq/test_axi_stream.py‎

Lines changed: 19 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -186,7 +186,7 @@
186186
(axis_maskaddr_13 == 2)? _saxi_resetval_2 :
187187
(axis_maskaddr_13 == 3)? _saxi_resetval_3 : 'hx;
188188
reg _saxi_cond_0_1;
189-
assign saxi_wready = _saxi_register_fsm == 2;
189+
assign saxi_wready = _saxi_register_fsm == 3;
190190
reg [32-1:0] th_comp;
191191
localparam th_comp_init = 0;
192192
reg signed [32-1:0] _th_comp_size_0;
@@ -340,16 +340,16 @@
340340
_saxi_register_3 <= axislite_resetval_16;
341341
_saxi_flag_3 <= 0;
342342
end
343-
if((_saxi_register_fsm == 2) && saxi_wvalid && (axis_maskaddr_13 == 0)) begin
343+
if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_13 == 0)) begin
344344
_saxi_register_0 <= saxi_wdata;
345345
end
346-
if((_saxi_register_fsm == 2) && saxi_wvalid && (axis_maskaddr_13 == 1)) begin
346+
if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_13 == 1)) begin
347347
_saxi_register_1 <= saxi_wdata;
348348
end
349-
if((_saxi_register_fsm == 2) && saxi_wvalid && (axis_maskaddr_13 == 2)) begin
349+
if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_13 == 2)) begin
350350
_saxi_register_2 <= saxi_wdata;
351351
end
352-
if((_saxi_register_fsm == 2) && saxi_wvalid && (axis_maskaddr_13 == 3)) begin
352+
if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_13 == 3)) begin
353353
_saxi_register_3 <= saxi_wdata;
354354
end
355355
if((_saxi_register_0 == 1) && (th_comp == 2) && 1) begin
@@ -401,6 +401,8 @@
401401
402402
localparam _saxi_register_fsm_1 = 1;
403403
localparam _saxi_register_fsm_2 = 2;
404+
localparam _saxi_register_fsm_3 = 3;
405+
localparam _saxi_register_fsm_4 = 4;
404406
405407
always @(posedge CLK) begin
406408
if(RST) begin
@@ -416,16 +418,26 @@
416418
_saxi_register_fsm <= _saxi_register_fsm_1;
417419
end
418420
if(writevalid_9) begin
419-
_saxi_register_fsm <= _saxi_register_fsm_2;
421+
_saxi_register_fsm <= _saxi_register_fsm_3;
420422
end
421423
end
422424
_saxi_register_fsm_1: begin
423425
if(saxi_rready || !saxi_rvalid) begin
424-
_saxi_register_fsm <= _saxi_register_fsm_init;
426+
_saxi_register_fsm <= _saxi_register_fsm_2;
425427
end
426428
end
427429
_saxi_register_fsm_2: begin
430+
if(saxi_rready && saxi_rvalid) begin
431+
_saxi_register_fsm <= _saxi_register_fsm_init;
432+
end
433+
end
434+
_saxi_register_fsm_3: begin
428435
if(saxi_wvalid) begin
436+
_saxi_register_fsm <= _saxi_register_fsm_4;
437+
end
438+
end
439+
_saxi_register_fsm_4: begin
440+
if(saxi_bready && saxi_bvalid) begin
429441
_saxi_register_fsm <= _saxi_register_fsm_init;
430442
end
431443
end

‎examples/stream_axi_stream_fifo_ipxact_ultra96v2_pynq/test_stream_axi_stream_fifo_ipxact.py‎

Lines changed: 23 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -287,7 +287,7 @@
287287
(axis_maskaddr_16 == 6)? _saxi_resetval_6 :
288288
(axis_maskaddr_16 == 7)? _saxi_resetval_7 : 'hx;
289289
reg _saxi_cond_0_1;
290-
assign saxi_wready = _saxi_register_fsm == 2;
290+
assign saxi_wready = _saxi_register_fsm == 3;
291291
wire _axi_in_read_req_fifo_enq;
292292
wire [41-1:0] _axi_in_read_req_fifo_wdata;
293293
wire _axi_in_read_req_fifo_full;
@@ -1154,28 +1154,28 @@
11541154
_saxi_register_7 <= axislite_resetval_19;
11551155
_saxi_flag_7 <= 0;
11561156
end
1157-
if((_saxi_register_fsm == 2) && saxi_wvalid && (axis_maskaddr_16 == 0)) begin
1157+
if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_16 == 0)) begin
11581158
_saxi_register_0 <= saxi_wdata;
11591159
end
1160-
if((_saxi_register_fsm == 2) && saxi_wvalid && (axis_maskaddr_16 == 1)) begin
1160+
if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_16 == 1)) begin
11611161
_saxi_register_1 <= saxi_wdata;
11621162
end
1163-
if((_saxi_register_fsm == 2) && saxi_wvalid && (axis_maskaddr_16 == 2)) begin
1163+
if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_16 == 2)) begin
11641164
_saxi_register_2 <= saxi_wdata;
11651165
end
1166-
if((_saxi_register_fsm == 2) && saxi_wvalid && (axis_maskaddr_16 == 3)) begin
1166+
if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_16 == 3)) begin
11671167
_saxi_register_3 <= saxi_wdata;
11681168
end
1169-
if((_saxi_register_fsm == 2) && saxi_wvalid && (axis_maskaddr_16 == 4)) begin
1169+
if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_16 == 4)) begin
11701170
_saxi_register_4 <= saxi_wdata;
11711171
end
1172-
if((_saxi_register_fsm == 2) && saxi_wvalid && (axis_maskaddr_16 == 5)) begin
1172+
if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_16 == 5)) begin
11731173
_saxi_register_5 <= saxi_wdata;
11741174
end
1175-
if((_saxi_register_fsm == 2) && saxi_wvalid && (axis_maskaddr_16 == 6)) begin
1175+
if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_16 == 6)) begin
11761176
_saxi_register_6 <= saxi_wdata;
11771177
end
1178-
if((_saxi_register_fsm == 2) && saxi_wvalid && (axis_maskaddr_16 == 7)) begin
1178+
if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_16 == 7)) begin
11791179
_saxi_register_7 <= saxi_wdata;
11801180
end
11811181
if((_saxi_register_0 == 1) && (th_comp == 2) && 1) begin
@@ -1271,6 +1271,8 @@
12711271
12721272
localparam _saxi_register_fsm_1 = 1;
12731273
localparam _saxi_register_fsm_2 = 2;
1274+
localparam _saxi_register_fsm_3 = 3;
1275+
localparam _saxi_register_fsm_4 = 4;
12741276
12751277
always @(posedge CLK) begin
12761278
if(RST) begin
@@ -1286,16 +1288,26 @@
12861288
_saxi_register_fsm <= _saxi_register_fsm_1;
12871289
end
12881290
if(writevalid_12) begin
1289-
_saxi_register_fsm <= _saxi_register_fsm_2;
1291+
_saxi_register_fsm <= _saxi_register_fsm_3;
12901292
end
12911293
end
12921294
_saxi_register_fsm_1: begin
12931295
if(saxi_rready || !saxi_rvalid) begin
1294-
_saxi_register_fsm <= _saxi_register_fsm_init;
1296+
_saxi_register_fsm <= _saxi_register_fsm_2;
12951297
end
12961298
end
12971299
_saxi_register_fsm_2: begin
1300+
if(saxi_rready && saxi_rvalid) begin
1301+
_saxi_register_fsm <= _saxi_register_fsm_init;
1302+
end
1303+
end
1304+
_saxi_register_fsm_3: begin
12981305
if(saxi_wvalid) begin
1306+
_saxi_register_fsm <= _saxi_register_fsm_4;
1307+
end
1308+
end
1309+
_saxi_register_fsm_4: begin
1310+
if(saxi_bready && saxi_bvalid) begin
12991311
_saxi_register_fsm <= _saxi_register_fsm_init;
13001312
end
13011313
end

‎examples/stream_axi_stream_fifo_ultra96v2_pynq/test_stream_axi_stream_fifo.py‎

Lines changed: 23 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -287,7 +287,7 @@
287287
(axis_maskaddr_16 == 6)? _saxi_resetval_6 :
288288
(axis_maskaddr_16 == 7)? _saxi_resetval_7 : 'hx;
289289
reg _saxi_cond_0_1;
290-
assign saxi_wready = _saxi_register_fsm == 2;
290+
assign saxi_wready = _saxi_register_fsm == 3;
291291
wire _axi_in_read_req_fifo_enq;
292292
wire [41-1:0] _axi_in_read_req_fifo_wdata;
293293
wire _axi_in_read_req_fifo_full;
@@ -1154,28 +1154,28 @@
11541154
_saxi_register_7 <= axislite_resetval_19;
11551155
_saxi_flag_7 <= 0;
11561156
end
1157-
if((_saxi_register_fsm == 2) && saxi_wvalid && (axis_maskaddr_16 == 0)) begin
1157+
if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_16 == 0)) begin
11581158
_saxi_register_0 <= saxi_wdata;
11591159
end
1160-
if((_saxi_register_fsm == 2) && saxi_wvalid && (axis_maskaddr_16 == 1)) begin
1160+
if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_16 == 1)) begin
11611161
_saxi_register_1 <= saxi_wdata;
11621162
end
1163-
if((_saxi_register_fsm == 2) && saxi_wvalid && (axis_maskaddr_16 == 2)) begin
1163+
if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_16 == 2)) begin
11641164
_saxi_register_2 <= saxi_wdata;
11651165
end
1166-
if((_saxi_register_fsm == 2) && saxi_wvalid && (axis_maskaddr_16 == 3)) begin
1166+
if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_16 == 3)) begin
11671167
_saxi_register_3 <= saxi_wdata;
11681168
end
1169-
if((_saxi_register_fsm == 2) && saxi_wvalid && (axis_maskaddr_16 == 4)) begin
1169+
if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_16 == 4)) begin
11701170
_saxi_register_4 <= saxi_wdata;
11711171
end
1172-
if((_saxi_register_fsm == 2) && saxi_wvalid && (axis_maskaddr_16 == 5)) begin
1172+
if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_16 == 5)) begin
11731173
_saxi_register_5 <= saxi_wdata;
11741174
end
1175-
if((_saxi_register_fsm == 2) && saxi_wvalid && (axis_maskaddr_16 == 6)) begin
1175+
if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_16 == 6)) begin
11761176
_saxi_register_6 <= saxi_wdata;
11771177
end
1178-
if((_saxi_register_fsm == 2) && saxi_wvalid && (axis_maskaddr_16 == 7)) begin
1178+
if((_saxi_register_fsm == 3) && saxi_wvalid && (axis_maskaddr_16 == 7)) begin
11791179
_saxi_register_7 <= saxi_wdata;
11801180
end
11811181
if((_saxi_register_0 == 1) && (th_comp == 2) && 1) begin
@@ -1271,6 +1271,8 @@
12711271
12721272
localparam _saxi_register_fsm_1 = 1;
12731273
localparam _saxi_register_fsm_2 = 2;
1274+
localparam _saxi_register_fsm_3 = 3;
1275+
localparam _saxi_register_fsm_4 = 4;
12741276
12751277
always @(posedge CLK) begin
12761278
if(RST) begin
@@ -1286,16 +1288,26 @@
12861288
_saxi_register_fsm <= _saxi_register_fsm_1;
12871289
end
12881290
if(writevalid_12) begin
1289-
_saxi_register_fsm <= _saxi_register_fsm_2;
1291+
_saxi_register_fsm <= _saxi_register_fsm_3;
12901292
end
12911293
end
12921294
_saxi_register_fsm_1: begin
12931295
if(saxi_rready || !saxi_rvalid) begin
1294-
_saxi_register_fsm <= _saxi_register_fsm_init;
1296+
_saxi_register_fsm <= _saxi_register_fsm_2;
12951297
end
12961298
end
12971299
_saxi_register_fsm_2: begin
1300+
if(saxi_rready && saxi_rvalid) begin
1301+
_saxi_register_fsm <= _saxi_register_fsm_init;
1302+
end
1303+
end
1304+
_saxi_register_fsm_3: begin
12981305
if(saxi_wvalid) begin
1306+
_saxi_register_fsm <= _saxi_register_fsm_4;
1307+
end
1308+
end
1309+
_saxi_register_fsm_4: begin
1310+
if(saxi_bready && saxi_bvalid) begin
12991311
_saxi_register_fsm <= _saxi_register_fsm_init;
13001312
end
13011313
end

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