simplified

Author: shtaxxx

examples/thread_myverilog_ipcore/test_thread_myverilog_ipcore.py

@@ -1086,6 +1086,9 @@
                   (_tmp_5 == 7)? _saxi_resetval_7 : 'hx;
   reg _saxi_cond_0_1;
   assign saxi_wready = _saxi_register_fsm == 2;
+  reg start;
+  wire busy;
+  reg [ADDR_WIDTH-1:0] size;
   wire pe_start;
   wire pe_busy;
   wire [ADDR_WIDTH-1+1-1:0] pe_size;
@@ -1103,9 +1106,9 @@
   (
     .CLK(CLK),
     .RST(RST),
-    .start(pe_start),
-    .busy(pe_busy),
-    .size(pe_size),
+    .start(start),
+    .busy(busy),
+    .size(size),
     .addr(pe_addr),
     .rdata(pe_rdata),
     .wdata(pe_wdata),
@@ -1134,12 +1137,6 @@
   end
 
   assign pe_rdata = ram_a_1_rdata;
-  reg start;
-  wire busy;
-  reg [ADDR_WIDTH-1:0] size;
-  assign pe_start = start;
-  assign pe_size = size;
-  assign busy = pe_busy;
   reg [32-1:0] th_memcpy;
   localparam th_memcpy_init = 0;
   reg signed [32-1:0] _th_memcpy_copy_bytes_0;

examples/thread_myverilog_ipcore/thread_myverilog_ipcore.py

@@ -113,28 +113,24 @@ def mkMemcpy():
 
     datawidth = m.Parameter('DATA_WIDTH', datawidth)
     addrwidth = m.Parameter('ADDR_WIDTH', addrwidth)
-    
-    # import verilog submodule 
+
+    # import verilog submodule
+    start = m.Reg('start', initval=0)
+    busy = m.Wire('busy')
+    size = m.Reg('size', addrwidth, initval=0)
+
     sub = Submodule(m, pe_verilog_code, 'inst_pe', prefix='pe_',
                     arg_params=(('ADDR_WIDTH', addrwidth),
                                 ('DATA_WIDTH', datawidth)),
-                    arg_ports=(('CLK', clk), ('RST', rst)),
+                    arg_ports=(('CLK', clk), ('RST', rst),
+                               ('start', start), ('busy', busy), ('size', size)),
                     as_wire=('start', 'busy', 'size',
                              'addr', 'rdata', 'wdata', 'wenable'))
 
     # connect ports to RAM
     ram_a.connect_rtl(1, sub['addr'], sub['wdata'],
                       sub['wenable'], sub['rdata'])
 
-    # control ports of submodule
-    start = m.Reg('start', initval=0)
-    busy = m.Wire('busy')
-    size = m.Reg('size', addrwidth, initval=0)
-
-    sub['start'].assign(start)
-    sub['size'].assign(size)
-    busy.assign(sub['busy'])
-
     def control_processing_unit(v):
         size.value = v
         start.value = 1