|
| 1 | +from __future__ import absolute_import |
| 2 | +from __future__ import print_function |
| 3 | + |
| 4 | +import veriloggen.types.fixed as fixed |
| 5 | + |
| 6 | + |
| 7 | +def _intrinsic_FixedInput(fsm, m, name, width=32, point=0, signed=True): |
| 8 | + return fixed.FixedInput(m, name, width=width, point=point, signed=signed) |
| 9 | + |
| 10 | + |
| 11 | +def _intrinsic_FixedOutput(fsm, m, name, width=32, point=0, signed=True): |
| 12 | + return fixed.FixedOutput(m, name, width=width, point=point, signed=signed) |
| 13 | + |
| 14 | + |
| 15 | +def _intrinsic_FixedOutputReg(fsm, m, name, width=32, point=0, signed=True): |
| 16 | + return fixed.FixedOutputReg(m, name, width=width, point=point, signed=signed) |
| 17 | + |
| 18 | + |
| 19 | +def _intrinsic_FixedReg(fsm, m, name, width=32, point=0, signed=True): |
| 20 | + return fixed.FixedReg(m, name, width=width, point=point, signed=signed) |
| 21 | + |
| 22 | + |
| 23 | +def _intrinsic_FixedWire(fsm, m, name, width=32, point=0, signed=True): |
| 24 | + return fixed.FixedWire(m, name, width=width, point=point, signed=signed) |
| 25 | + |
| 26 | + |
| 27 | +def _intrinsic_to_fixed(fsm, value, point, signed=False): |
| 28 | + return fixed.to_fixed(value, point, signed) |
| 29 | + |
| 30 | + |
| 31 | +def _intrinsic_fixed_to_int(fsm, value, point, signed=False): |
| 32 | + return fixed.fixed_to_int(value, point, signed) |
| 33 | + |
| 34 | + |
| 35 | +def _intrinsic_fixed_to_int_low(fsm, value, point): |
| 36 | + return fixed.fixed_to_int_low(value, point) |
| 37 | + |
| 38 | + |
| 39 | +def _intrinsic_fixed_to_real(fsm, value, point, signed=False): |
| 40 | + return fixed.fixed_to_real(value, point, signed) |
0 commit comments