types.util.connect_port() is replaced.

Author: shtaxxx

veriloggen/core/vtypes.py

@@ -432,7 +432,7 @@ def connect(self, value):
             wire_self = self.module.TmpWireLike(self)
             wire_self.assign(value)
             self.module.Always()(self(wire_self, blk=True))
-        elif isinstance(self, Wire):
+        elif isinstance(self, (Wire, Output)):
             self.assign(value)
         else:
             raise TypeError('connect() is not supported')

veriloggen/types/fifo.py

@@ -34,10 +34,10 @@ def __init__(self, m, name=None, datawidth=32, itype=None, otype=None,
             m, otype, name_almost_full, initval=0)
 
     def connect(self, targ):
-        util.connect_port(self.enq, targ.enq)
-        util.connect_port(self.wdata, targ.wdata)
-        util.connect_port(targ.full, self.full)
-        util.connect_port(targ.almost_full, self.almost_full)
+        self.enq.connect(targ.enq)
+        self.wdata.connect(targ.wdata)
+        targ.full.connect(self.full)
+        targ.almost_full.connect(self.almost_full)
 
 
 class FifoReadInterface(object):
@@ -67,10 +67,10 @@ def __init__(self, m, name=None, datawidth=32, itype=None, otype=None,
             m, otype, name_almost_empty, initval=0)
 
     def connect(self, targ):
-        util.connect_port(self.deq, targ.deq)
-        util.connect_port(targ.rdata, self.rdata)
-        util.connect_port(targ.empty, self.empty)
-        util.connect_port(targ.almost_empty, self.almost_empty)
+        self.deq.connect(targ.deq)
+        targ.rdata.connect(self.rdata)
+        targ.empty.connect(self.empty)
+        targ.almost_empty.connect(self.almost_empty)
 
 
 class FifoWriteSlaveInterface(FifoWriteInterface):

veriloggen/types/ram.py

@@ -52,15 +52,15 @@ def __init__(self, m, name=None, datawidth=32, addrwidth=10,
             self.enable = util.make_port(m, itype, name_enable, initval=0)
 
     def connect(self, targ):
-        util.connect_port(self.addr, targ.addr)
-        util.connect_port(targ.rdata, self.rdata)
-        util.connect_port(self.wdata, targ.wdata)
-        util.connect_port(self.wenable, targ.wenable)
+        self.addr.connect(targ.addr)
+        targ.rdata.connect(self.rdata)
+        self.wdata.connect(targ.wdata)
+        self.wenable.connect(targ.wenable)
         if hasattr(self, 'enable'):
             if hasattr(targ, 'enable'):
-                util.connect_port(self.enable, targ.enable)
+                self.enable.connect(targ.enable)
             else:
-                util.connect_port(self.enable, 1)
+                self.enable.connect(1)
         else:
             if hasattr(targ, 'enable'):
                 raise ValueError('no enable port')