Skip to content

Commit 44c4149

Browse files
committed
mul.reset() is called in reset() method.
1 parent 19cc5c0 commit 44c4149

File tree

1 file changed

+1
-2
lines changed

1 file changed

+1
-2
lines changed

veriloggen/dataflow/dataflow.py

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@ def reset():
2525
global _dataflow_counter
2626
_dataflow_counter = 0
2727
dtypes._object_counter = 0
28+
mul.reset()
2829

2930

3031
def DataflowManager(module, clock, reset, no_hook=False):
@@ -81,8 +82,6 @@ def to_module(self, name, clock='CLK', reset='RST'):
8182
def implement(self, m=None, clock=None, reset=None, seq_name=None, aswire=True):
8283
""" implemente actual registers and operations in Verilog """
8384

84-
mul.reset()
85-
8685
if m is None:
8786
m = self.module
8887

0 commit comments

Comments
 (0)