Merge branch 'develop' into 2.3.0-rc

Author: shtaxxx

examples/thread_matmul_ext_onchip_ram/thread_matmul_ext_onchip_ram.py

@@ -3,6 +3,7 @@
 import sys
 import os
 import numpy as np
+import math
 
 # the next line can be removed after installation
 sys.path.insert(0, os.path.dirname(os.path.dirname(
@@ -12,13 +13,23 @@
 import veriloggen.thread as vthread
 import veriloggen.types.axi as axi
 
-datawidth = 8
+mem_datawidth = 8
+datawidth = 16
 addrwidth = 8
 
-matrix_size = 8
+matrix_size = 10
+
+num_pack = math.ceil(datawidth / mem_datawidth)
+addr_pack = math.ceil((addrwidth + math.ceil(np.log2(datawidth / mem_datawidth)))
+                       / mem_datawidth)
+
+matrix_size_addr = 0
+a_offset_addr = 4
+b_offset_addr = 8
+c_offset_addr = 12
 a_offset = 16
-b_offset = a_offset + matrix_size * matrix_size
-c_offset = b_offset + matrix_size * matrix_size
+b_offset = a_offset + matrix_size * matrix_size * num_pack
+c_offset = b_offset + matrix_size * matrix_size * num_pack
 
 
 def mkLed():
@@ -28,7 +39,8 @@ def mkLed():
     start = m.Input('start')
     busy = m.OutputReg('busy', initval=0)
 
-    ram = vthread.ExtRAM(m, 'ram', clk, rst, datawidth, addrwidth)
+    ram = vthread.ExtRAM(m, 'ram', clk, rst, mem_datawidth, 
+                         addrwidth + math.ceil(np.log2(datawidth / mem_datawidth)))
 
     def matmul():
         while True:
@@ -46,27 +58,31 @@ def wait():
         busy.value = 1
 
     def read_matrix_size():
-        size0 = ram.read(0)
-        size1 = ram.read(1)
-        size = (size1 << 8) | size0
+        size = 0
+        for i in range(addr_pack):
+            size |= ((ram.read(matrix_size_addr + i) & ((1 << mem_datawidth) - 1))
+                     << (mem_datawidth * i))
         return size
 
     def read_matrix_a_offset():
-        offset0 = ram.read(4) & 0xff
-        offset1 = ram.read(5) & 0xff
-        offset = (offset1 << 8) | offset0
+        offset = 0
+        for i in range(addr_pack):
+            offset |= ((ram.read(a_offset_addr + i) & ((1 << mem_datawidth) - 1))
+                       << (mem_datawidth * i))
         return offset
 
     def read_matrix_b_offset():
-        offset0 = ram.read(8) & 0xff
-        offset1 = ram.read(9) & 0xff
-        offset = (offset1 << 8) | offset0
+        offset = 0
+        for i in range(addr_pack):
+            offset |= ((ram.read(b_offset_addr + i) & ((1 << mem_datawidth) - 1))
+                       << (mem_datawidth * i))
         return offset
 
     def read_matrix_c_offset():
-        offset0 = ram.read(12) & 0xff
-        offset1 = ram.read(13) & 0xff
-        offset = (offset1 << 8) | offset0
+        offset = 0
+        for i in range(addr_pack):
+            offset |= ((ram.read(c_offset_addr + i) & ((1 << mem_datawidth) - 1))
+                       << (mem_datawidth * i))
         return offset
 
     def comp(matrix_size, a_offset, b_offset, c_offset):
@@ -77,15 +93,24 @@ def comp(matrix_size, a_offset, b_offset, c_offset):
             for j in range(matrix_size):
                 sum = 0
                 for k in range(matrix_size):
-                    x = ram.read(a_addr + k)
-                    y = ram.read(b_addr + k)
+                    x = int(0, base=2)
+                    y = 0
+                    for l in range(num_pack):
+                        x |= ((ram.read(a_addr + k * num_pack + l) 
+                               & ((1 << mem_datawidth) - 1))
+                              << (mem_datawidth * l))
+                        y |= ((ram.read(b_addr + k * num_pack + l) 
+                               & ((1 << mem_datawidth) - 1)) 
+                              << (mem_datawidth * l))
                     sum += x * y
-                ram.write(c_addr + j, sum)
+                for l in range(num_pack):
+                    ram.write(c_addr + j * num_pack + l,
+                              (sum >> (mem_datawidth * l)) & (1<<mem_datawidth)-1)
 
-                b_addr += matrix_size * (datawidth // 8)
+                b_addr += matrix_size * num_pack
 
-            a_addr += matrix_size * (datawidth // 8)
-            c_addr += matrix_size * (datawidth // 8)
+            a_addr += matrix_size * num_pack
+            c_addr += matrix_size * num_pack
 
     def done():
         busy.value = 0
@@ -128,13 +153,11 @@ def mkTest(memimg_name=None):
                 b[y][x] = 0
 
     a_addr = a_offset
-    size_a = n_a * datawidth // 8
     b_addr = b_offset
-    size_b = n_b * datawidth // 8
 
-    mem = np.zeros([2 ** addrwidth * (8 // datawidth)], dtype=np.int64)
-    axi.set_memory(mem, a, datawidth, datawidth, a_addr)
-    axi.set_memory(mem, b, datawidth, datawidth, b_addr)
+    mem = np.zeros([(2 ** addrwidth) * num_pack], dtype=np.int64)
+    axi.set_memory(mem, a, mem_datawidth, datawidth, a_addr)
+    axi.set_memory(mem, b, mem_datawidth, datawidth, b_addr)
 
     led = mkLed()
 
@@ -149,7 +172,8 @@ def mkTest(memimg_name=None):
 
     start.initval = 0
 
-    memory = vthread.RAM(m, 'memory', clk, rst, datawidth, addrwidth,
+    memory = vthread.RAM(m, 'memory', clk, rst, mem_datawidth, 
+                         addrwidth + math.ceil(np.log2(datawidth / mem_datawidth)),
                          numports=2, initvals=mem.tolist())
     memory.connect_rtl(0, ports['ram_0_addr'], ports['ram_0_wdata'],
                        ports['ram_0_wenable'], ports['ram_0_rdata'],
@@ -166,45 +190,33 @@ def ctrl():
         for i in range(100):
             pass
 
-        awaddr = 0
-        v = (matrix_size & 0xff)
-        print('# matrix_size[7:0] = %d' % v)
-        memory.write(awaddr, v, port=1)
-
-        awaddr = 1
-        v = ((matrix_size >> 8) & 0xff)
-        print('# matrix_size[15:8] = %d' % v)
-        memory.write(awaddr, v, port=1)
-
-        awaddr = 4
-        v = (a_offset & 0xff)
-        print('# a_offset[7:0] = %d' % v)
-        memory.write(awaddr, v, port=1)
-
-        awaddr = 5
-        v = ((a_offset >> 8) & 0xff)
-        print('# a_offset[15:8] = %d' % v)
-        memory.write(awaddr, v, port=1)
-
-        awaddr = 8
-        v = (b_offset & 0xff)
-        print('# b_offset[7:0] = %d' % v)
-        memory.write(awaddr, v, port=1)
-
-        awaddr = 9
-        v = ((b_offset >> 8) & 0xff)
-        print('# b_offset[15:8] = %d' % v)
-        memory.write(awaddr, v, port=1)
-
-        awaddr = 12
-        v = (c_offset & 0xff)
-        print('# c_offset[7:0] = %d' % v)
-        memory.write(awaddr, v, port=1)
-
-        awaddr = 13
-        v = ((c_offset >> 8) & 0xff)
-        print('# c_offset[15:8] = %d' % v)
-        memory.write(awaddr, v, port=1)
+        for i in range(addr_pack):
+            awaddr = matrix_size_addr + i
+            v = (matrix_size >> (mem_datawidth * i)) & ((1 << mem_datawidth) - 1)
+            print('# matrix_size[%d:%d] = %d' % 
+                  (mem_datawidth * (i+1) - 1, mem_datawidth * i, v))
+            memory.write(awaddr, v, port=1)
+
+        for i in range(addr_pack):
+            awaddr = a_offset_addr + i
+            v = (a_offset >> (mem_datawidth * i)) & ((1 << mem_datawidth) - 1)
+            print('# a_offset[%d:%d] = %d' % 
+                  (mem_datawidth * (i+1) - 1, mem_datawidth * i, v))
+            memory.write(awaddr, v, port=1)
+
+        for i in range(addr_pack):
+            awaddr = b_offset_addr + i
+            v = (b_offset >> (mem_datawidth * i)) & ((1 << mem_datawidth) - 1)
+            print('# b_offset[%d:%d] = %d' % 
+                  (mem_datawidth * (i+1) - 1, mem_datawidth * i, v))
+            memory.write(awaddr, v, port=1)
+
+        for i in range(addr_pack):
+            awaddr = c_offset_addr + i
+            v = (c_offset >> (mem_datawidth * i)) & ((1 << mem_datawidth) - 1)
+            print('# c_offset[%d:%d] = %d' % 
+                  (mem_datawidth * (i+1) - 1, mem_datawidth * i, v))
+            memory.write(awaddr, v, port=1)
 
         start_time = counter
         print('# start time = %d' % start_time)
@@ -227,14 +239,19 @@ def ctrl():
         all_ok = True
         for y in range(matrix_size):
             for x in range(matrix_size):
-                v = memory.read(
-                    c_offset + (y * matrix_size + x) * datawidth // 8, port=1)
+                v = 0
+                v_addr = c_offset + (y * matrix_size + x) * num_pack
+                for l in range(num_pack):
+                    v |= memory.read(v_addr + l, port=1) << (mem_datawidth * l)
+                    v |= ((memory.read(v_addr + l, port=1) 
+                           & ((1 << mem_datawidth) - 1))
+                          << (mem_datawidth * l))
                 if y == x and vthread.verilog.NotEql(v, (y + 1) * 2):
                     all_ok = False
-                    print("NG [%d,%d] = %d" % (y, x, v))
+                    print("NG [%d,%d] = %d (expected: %d)" % (y, x, v, (y + 1) * 2))
                 if y != x and vthread.verilog.NotEql(v, 0):
                     all_ok = False
-                    print("NG [%d,%d] = %d" % (y, x, v))
+                    print("NG [%d,%d] = %d (expected: %d)" % (y, x, v, 0))
 
         if all_ok:
             print('# verify: PASSED')

tests/core/stub_/str/stub_str.py

@@ -11,19 +11,14 @@
 from veriloggen import *
 
 
-def mkLed():
-    m = StubModule('blinkled')
-    return m
-
-
 def mkTop():
     m = Module('top')
     width = m.Parameter('WIDTH', 8)
     clk = m.Input('CLK')
     rst = m.Input('RST')
     led = m.Output('LED', width)
 
-    params = (width, )
+    params = (width,)
     ports = (clk, rst, led)
 
     # StubModule is automatically created inside

tests/core/stub_/str_multiple/Makefile

@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v *.vcd

tests/core/stub_/str_multiple/stub_str_multiple.py

@@ -0,0 +1,36 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+import collections
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+
+
+def mkTop():
+    m = Module('top')
+    width = m.Parameter('WIDTH', 8)
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    led0 = m.Output('LED0', width)
+    led1 = m.Output('LED1', width)
+
+    params0 = (width,)
+    ports0 = (clk, rst, led0)
+    m.Instance('blinkled', 'inst_blinkled0', params0, ports0)
+
+    params1 = (width,)
+    ports1 = (clk, rst, led1)
+    m.Instance('blinkled', 'inst_blinkled1', params0, ports1)
+
+    return m
+
+
+if __name__ == '__main__':
+    top = mkTop()
+    verilog = top.to_verilog()
+    print(verilog)

tests/core/stub_/str_multiple/test_stub_str_multiple.py

@@ -0,0 +1,60 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import veriloggen
+import stub_str_multiple
+
+
+expected_verilog = """
+module top #
+(
+  parameter WIDTH = 8
+)
+(
+  input CLK,
+  input RST,
+  output [WIDTH-1:0] LED0,
+  output [WIDTH-1:0] LED1
+);
+
+
+  blinkled
+  #(
+    WIDTH
+  )
+  inst_blinkled0
+  (
+    CLK,
+    RST,
+    LED0
+  );
+
+
+  blinkled
+  #(
+    WIDTH
+  )
+  inst_blinkled1
+  (
+    CLK,
+    RST,
+    LED1
+  );
+
+
+endmodule
+"""
+
+
+def test():
+    veriloggen.reset()
+    test_module = stub_str_multiple.mkTop()
+    code = test_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(expected_code == code)