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lib_simulation test is updated.
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4 files changed

+16
-9
lines changed

4 files changed

+16
-9
lines changed

tests/lib_simulation_/basic/lib_simulation_basic.py

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@@ -1,5 +1,9 @@
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import sys
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import os
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# the next line can be removed after installation
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sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
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from veriloggen import *
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def mkLed():

tests/lib_simulation_/basic/test_lib_simulation_basic.py

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import led
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import lib_simulation_basic
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expected_verilog = """
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module test #
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endmodule
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"""
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def test_led():
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test_module = led.mkTest()
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test_code = test_module.to_verilog()
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def test():
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test_module = lib_simulation_basic.mkTest()
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code = test_module.to_verilog()
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from pyverilog.vparser.parser import VerilogParser
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from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
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codegen = ASTCodeGenerator()
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expected_code = codegen.visit(expected_ast)
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assert(expected_code == test_code)
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assert(expected_code == code)

tests/lib_simulation_/pycoram_userlogic/lib_simulation_pycoram_userlogic.py

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import os
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import collections
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# the next line can be removed after installation
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sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))
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from veriloggen import *
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def mkUserlogic():

tests/lib_simulation_/pycoram_userlogic/test_lib_simulation_pycoram_userlogic.py

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import led
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import lib_simulation_pycoram_userlogic
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expected_verilog = """
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module test #
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endmodule
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"""
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def test_led():
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test = led.mkTest()
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code = test.to_verilog()
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def test():
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test_module = lib_simulation_pycoram_userlogic.mkTest()
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code = test_module.to_verilog()
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from pyverilog.vparser.parser import VerilogParser
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from pyverilog.ast_code_generator.codegen import ASTCodeGenerator

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