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Merge branch 'develop' into 2.1.0-rc
2 parents e4d3982 + c7fe4c5 commit 3e87880

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5 files changed

+59
-27
lines changed

5 files changed

+59
-27
lines changed

‎tests/core/instance_/multiple_instances/multiple_instances.py‎

Lines changed: 30 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,12 @@
55
import collections
66

77
# the next line can be removed after installation
8-
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
8+
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
9+
os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
910

1011
from veriloggen import *
1112

13+
1214
def mkLed():
1315
m = Module('blinkled')
1416
width = m.Parameter('WIDTH', 8)
@@ -27,41 +29,53 @@ def mkLed():
2729
count(count + 1)
2830
)
2931
))
30-
32+
3133
m.Always(Posedge(clk))(
3234
If(rst)(
33-
led( 0 )
35+
led(0)
3436
).Else(
3537
If(count == 1023)(
36-
led( led + 1 )
38+
led(led + 1)
3739
)
3840
))
3941

4042
return m
4143

44+
4245
def mkTop():
4346
m = Module('top')
4447
led = mkLed()
4548

4649
clk = m.Input('CLK')
4750
rst = m.Input('RST')
48-
49-
params = m.copy_params(led, prefix='A_')
50-
ports = m.copy_ports(led, prefix='A_', exclude=('CLK', 'RST'))
51-
52-
params = m.copy_params(led, prefix='B_')
53-
ports = m.copy_ports(led, prefix='B_', exclude=('CLK', 'RST'))
54-
51+
52+
m.copy_params(led, prefix='A_')
53+
m.copy_ports(led, prefix='A_', exclude=('CLK', 'RST'))
54+
55+
m.copy_params(led, prefix='B_')
56+
m.copy_ports(led, prefix='B_', exclude=('CLK', 'RST'))
57+
58+
a_params = m.connect_params(led, prefix='A_')
59+
a_ports = collections.OrderedDict()
60+
a_ports['CLK'] = clk
61+
a_ports['RST'] = rst
62+
a_ports.update(m.connect_ports(led, prefix='A_'))
63+
64+
b_params = m.connect_params(led, prefix='B_')
65+
b_ports = collections.OrderedDict()
66+
b_ports['CLK'] = clk
67+
b_ports['RST'] = rst
68+
b_ports.update(m.connect_ports(led, prefix='B_'))
69+
5570
m.Instance(led, 'inst_blinkled_a',
56-
m.connect_params(led, prefix='A_'),
57-
m.connect_ports(led, prefix='') + m.connect_ports(led, prefix='A_'))
58-
71+
params=a_params, ports=a_ports)
72+
5973
m.Instance(led, 'inst_blinkled_b',
60-
m.connect_params(led, prefix='B_'),
61-
m.connect_ports(led, prefix='') + m.connect_ports(led, prefix='B_'))
74+
params=b_params, ports=b_ports)
6275

6376
return m
6477

78+
6579
if __name__ == '__main__':
6680
top = mkTop()
6781
verilog = top.to_verilog()

‎veriloggen/core/module.py‎

Lines changed: 12 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -921,7 +921,9 @@ def copy_sim_ports(self, src, prefix=None, postfix=None,
921921

922922
# -------------------------------------------------------------------------
923923
def connect_params(self, targ, prefix=None, postfix=None,
924-
include=None, exclude=None, strict=False):
924+
include=None, exclude=None, strict=False,
925+
use_fullmatch=False):
926+
925927
if prefix is None:
926928
prefix = ''
927929
if postfix is None:
@@ -934,7 +936,7 @@ def connect_params(self, targ, prefix=None, postfix=None,
934936
exclude = ()
935937
if isinstance(exclude, str):
936938
exclude = [exclude]
937-
ret = []
939+
ret = collections.OrderedDict()
938940
for key, obj in targ.global_constant.items():
939941
if not include:
940942
skip = False
@@ -958,13 +960,15 @@ def connect_params(self, targ, prefix=None, postfix=None,
958960
raise IndexError(
959961
"No such constant '%s' in module '%s'" % (key, self.name))
960962
if my_key in self.global_constant:
961-
ret.append((key, self.global_constant[my_key]))
963+
ret[key] = self.global_constant[my_key]
962964
elif my_key in self.local_constant:
963-
ret.append((key, self.local_constant[my_key]))
965+
ret[key] = self.local_constant[my_key]
964966
return ret
965967

966968
def connect_ports(self, targ, prefix=None, postfix=None,
967-
include=None, exclude=None, strict=False):
969+
include=None, exclude=None, strict=False,
970+
use_fullmatch=False):
971+
968972
if prefix is None:
969973
prefix = ''
970974
if postfix is None:
@@ -977,7 +981,7 @@ def connect_ports(self, targ, prefix=None, postfix=None,
977981
exclude = ()
978982
if isinstance(exclude, str):
979983
exclude = [exclude]
980-
ret = []
984+
ret = collections.OrderedDict()
981985
for key, obj in targ.io_variable.items():
982986
if not include:
983987
skip = False
@@ -1001,9 +1005,9 @@ def connect_ports(self, targ, prefix=None, postfix=None,
10011005
raise IndexError("No such IO '%s' in module '%s'" %
10021006
(key, self.name))
10031007
if my_key in self.io_variable:
1004-
ret.append((key, self.io_variable[my_key]))
1008+
ret[key] = self.io_variable[my_key]
10051009
elif my_key in self.variable:
1006-
ret.append((key, self.variable[my_key]))
1010+
ret[key] = self.variable[my_key]
10071011
return ret
10081012

10091013
# -------------------------------------------------------------------------

‎veriloggen/thread/fifo.py‎

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,8 @@
11
from __future__ import absolute_import
22
from __future__ import print_function
33

4+
import collections
5+
46
import veriloggen.core.vtypes as vtypes
57
import veriloggen.types.util as util
68
import veriloggen.types.fixed as fxd
@@ -37,8 +39,12 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=4, sync=True):
3739

3840
self.definition = mkFifoDefinition(name, datawidth, addrwidth, sync=sync)
3941

42+
ports = collections.OrderedDict()
43+
ports['CLK'] = self.clk
44+
ports['RST'] = self.rst
45+
ports.update(m.connect_ports(self.definition))
4046
self.inst = self.m.Instance(self.definition, 'inst_' + name,
41-
ports=m.connect_ports(self.definition))
47+
ports=ports)
4248

4349
self.seq = Seq(m, name, clk, rst)
4450

‎veriloggen/thread/ram.py‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,7 @@
33

44
import functools
55
import math
6+
import collections
67

78
import veriloggen.core.vtypes as vtypes
89
import veriloggen.types.fixed as fxd
@@ -64,8 +65,11 @@ def __init__(self, m, name, clk, rst,
6465
nocheck_initvals=nocheck_initvals,
6566
ram_style=ram_style)
6667

68+
ports = collections.OrderedDict()
69+
ports['CLK'] = self.clk
70+
ports.update(m.connect_ports(self.definition))
6771
self.inst = self.m.Instance(self.definition, 'inst_' + name,
68-
ports=m.connect_ports(self.definition))
72+
ports=ports)
6973

7074
self.seq = Seq(m, name, clk, rst)
7175

‎veriloggen/types/ram.py‎

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@
22
from __future__ import print_function
33

44
import copy
5+
import collections
56
import veriloggen.core.vtypes as vtypes
67
from veriloggen.core.module import Module
78
from . import util
@@ -177,8 +178,11 @@ def __init__(self, m, name, clk,
177178
ram_def = mkRAMDefinition(name, datawidth, addrwidth, numports,
178179
initvals, sync, with_enable)
179180

181+
ports = collections.OrderedDict()
182+
ports['CLK'] = self.clk
183+
ports.update(m.connect_ports(ram_def))
180184
self.m.Instance(ram_def, name,
181-
params=(), ports=m.connect_ports(ram_def))
185+
params=(), ports=ports)
182186

183187
def connect(self, port, addr, wdata, wenable, enable=None):
184188
self.m.Assign(self.interfaces[port].addr(addr))

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