Merge branch 'develop'

Author: shtaxxx

veriloggen/core/module.py

@@ -1069,6 +1069,15 @@ def add_object(self, obj):
             self.generate[obj.true_scope] = obj
             return
 
+        if isinstance(obj, GenerateIfElse):
+            if obj.false_scope is None:
+                if None not in self.generate:
+                    self.generate[None] = []
+                self.generate[None].append(obj)
+                return
+            self.generate[obj.false_scope] = obj
+            return
+
         if isinstance(obj, Instance):
             if isinstance(obj.module, Module):
                 self.instance[obj.instname] = obj

veriloggen/core/vtypes.py

@@ -2099,7 +2099,11 @@ def __init__(self, *args):
             raise ValueError("Scope requires at least one argument.")
 
     def bit_length(self):
-        return self.args[-1].bit_length()
+        try:
+            w = self.args[-1].bit_length()
+            return w
+        except:
+            raise ValueError('could not identify bit_length.')
 
 
 class SystemTask(_Numeric):

veriloggen/resolver/resolver.py

@@ -104,7 +104,7 @@ def __init__(self, const_dict):
         _CommonVisitor.__init__(self)
         self.const_dict = const_dict
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def get_const(self, name):
         if name not in self.const_dict:
             raise KeyError("No such constant: '%s'" % name)
@@ -119,7 +119,7 @@ def update_const(self, name, value):
     def get_const_dict(self):
         return self.const_dict
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def _visit_param(self, node):
         if self.has_const(node.name):
             value = self.get_const(node.name)
@@ -136,7 +136,7 @@ def visit_Localparam(self, node):
     def visit_AnyType(self, node):
         return self._visit_param(node)
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def visit__BinaryOperator(self, node):
         left = self.visit(node.left)
         right = self.visit(node.right)
@@ -157,7 +157,7 @@ def visit__UnaryOperator(self, node):
             return node.op(right, rwidth)
         return node
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def visit_Pointer(self, node):
         var = self.visit(node.var)
         pos = self.visit(node.pos)
@@ -215,7 +215,7 @@ def visit_tuple(self, node):
     def visit_list(self, node):
         return [self.visit(n) for n in node]
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def visit__BinaryOperator(self, node):
         left = self.visit(node.left)
         right = self.visit(node.right)
@@ -311,7 +311,7 @@ def visit_Cond(self, node):
             node.false_value = false_value
         return node
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def visit_Posedge(self, node):
         name = self.visit(node.name)
         if check_overwrite(name):
@@ -327,7 +327,7 @@ def visit_Negedge(self, node):
     def visit_SensitiveAll(self, node):
         return node
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def visit_Subst(self, node):
         left = self.visit(node.left)
         right = self.visit(node.right)
@@ -342,7 +342,7 @@ def visit_Subst(self, node):
             node.rdelay = rdelay
         return node
 
-    #-------------------------------------------------------------------------
+    # -------------------------------------------------------------------------
     def visit_If(self, node):
         condition = self.visit(node.condition)
         true_statement = self.visit(node.true_statement)
@@ -665,12 +665,14 @@ def visit_Instance(self, node):
         return node
 
     def visit_GenerateFor(self, node):
-        raise NotImplementedError(
-            "GenerateFor statement is not currently supported.")
+        # raise NotImplementedError(
+        #    "GenerateFor statement is not currently supported.")
+        return node
 
     def visit_GenerateIf(self, node):
-        raise NotImplementedError(
-            "GenerateIf statement is not currently supported.")
+        # raise NotImplementedError(
+        #    "GenerateIf statement is not currently supported.")
+        return node
 
 
 def resolve(m, const_dict=None):

veriloggen/verilog/from_verilog.py

@@ -16,9 +16,9 @@
 from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
 
 
-#-------------------------------------------------------------------------
+# -------------------------------------------------------------------------
 # User interfaces to read Verilog source code
-#-------------------------------------------------------------------------
+# -------------------------------------------------------------------------
 def read_verilog_stubmodule(*filelist, **opt):
     module_dict = to_module_dict(*filelist, **opt)
     codegen = ASTCodeGenerator()
@@ -60,7 +60,7 @@ def read_verilog_stubmodule_str(code, encode='utf-8'):
     return ret
 
 
-#-------------------------------------------------------------------------
+# -------------------------------------------------------------------------
 def to_module_dict(*filelist, **opt):
     ast = to_ast(*filelist, **opt)
 
@@ -75,7 +75,7 @@ def to_module_dict(*filelist, **opt):
     return module_dict
 
 
-#-------------------------------------------------------------------------
+# -------------------------------------------------------------------------
 def to_ast(*filelist, **opt):
     include = opt['include'] if 'include' in opt else ()
     define = opt['define'] if 'define' in opt else ()
@@ -94,14 +94,14 @@ def to_ast(*filelist, **opt):
     return ast
 
 
-#-------------------------------------------------------------------------
+# -------------------------------------------------------------------------
 def to_tuple(s):
     if not isinstance(s, (list, tuple)):
         return tuple([s])
     return s
 
 
-#-------------------------------------------------------------------------
+# -------------------------------------------------------------------------
 class ReadOnlyModule(object):
 
     def __init__(self, m):
@@ -111,7 +111,7 @@ def __getattr__(self, attr):
         return getattr(self.m, attr)
 
 
-#-------------------------------------------------------------------------
+# -------------------------------------------------------------------------
 class VerilogReadVisitor(object):
 
     def __init__(self, ast_module_dict, converted_modules=None):
@@ -217,10 +217,29 @@ def visit_Length(self, node):
     def visit_Identifier(self, node):
         if node.scope is not None:
             labels = self.visit(node.scope)
-            labels.append(node.name)
+
+            if not isinstance(self.m, (module.Module, ReadOnlyModule)):
+                lables.append(vtypes.AnyType(name=node.name))
+                return vtypes.Scope(*labels)
+
+            m = self.m
+            for label in labels:
+                name = label.name if isinstance(label, vtypes.ScopeIndex) else label
+                m = m.find_identifier(name)
+
+            v = m.find_identifier(node.name)
+            if v is None:
+                labels.append(vtypes.AnyType(name=node.name))
+            elif v.name in m.variable:
+                labels.append(m.variable[v.name])
+            else:
+                labels.append(v)
+
             return vtypes.Scope(*labels)
+
         if not isinstance(self.m, (module.Module, ReadOnlyModule)):
             return vtypes.AnyType(name=node.name)
+
         ret = self.m.find_identifier(node.name)
         if ret is None:
             return vtypes.AnyType(name=node.name)
@@ -892,6 +911,7 @@ def _visit_GenerateIf(self, item):
         statement = self.visit(item.true_statement)
         self.pop_module()
         _if_false = _if_true.Else(false_scope)
+        self.add_object(_if_false)
         self.push_module(_if_false)
         statement = (self.visit(item.false_statement)
                      if item.false_statement is not None else None)

veriloggen/verilog/to_verilog.py

@@ -837,6 +837,9 @@ def visit_GenerateIf(self, node):
         _if = vast.IfStatement(cond, true_block, false_block)
         return vast.GenerateStatement(tuple([_if]))
 
+    def visit_GenerateIfElse(self, node):
+        return None
+
 
 #-------------------------------------------------------------------------
 class VerilogBindVisitor(VerilogCommonVisitor):