Example in README is updated

Author: shtaxxx

README.md

@@ -127,48 +127,45 @@ Run the script.
 python led.py
 ```
 
-You will have a complete Verilog HDL source code that is generated by a source code generator of Pyverilog.
-Currently a source code generated by Pyverilog has no good indentation. Please prettify it by using a standard text editor.
+You will have a complete Verilog HDL source code that is generated by the source code generator of Pyverilog.
 
 ```verilog
 module blinkled #
- (
+(
   parameter WIDTH = 8
+)
+(
+  input CLK,
+  input RST,
+  output reg [(WIDTH - 1):0] LED
+);
 
- )
- (
-  input [0:0] CLK, 
-input [0:0] RST, 
-output reg [(WIDTH - 1):0] LED
-
- );
   reg [(32 - 1):0] count;
-  always @(posedge CLK)
-  begin        
-  if(RST) begin        
-  count <= 0;
-end  
-else begin        
-  if((count == 1023)) begin        
-  count <= 0;
-end  
-else begin        
-  count <= (count + 1);
-end 
-end 
-end 
-  always @(posedge CLK)
-  begin        
-  if(RST) begin        
-  LED <= 0;
-end  
-else begin        
-  if((count == 1023)) begin        
-  LED <= (LED + 1);
-end  
-
-end 
-end 
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      count <= 0;
+    end else begin
+      if((count == 1023)) begin
+        count <= 0;
+      end else begin
+        count <= (count + 1);
+      end
+    end
+  end
+
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      LED <= 0;
+    end else begin
+      if((count == 1023)) begin
+        LED <= (LED + 1);
+      end 
+    end
+  end
+
+
 endmodule
 ```
 

README.rst

@@ -144,51 +144,47 @@ Run the script.
 
     python led.py
 
-You will have a complete Verilog HDL source code that is generated by a
-source code generator of Pyverilog. Currently a source code generated by
-Pyverilog has no good indentation. Please prettify it by using a
-standard text editor.
+You will have a complete Verilog HDL source code that is generated by
+the source code generator of Pyverilog.
 
 .. code:: verilog
 
     module blinkled #
-     (
+    (
       parameter WIDTH = 8
+    )
+    (
+      input CLK,
+      input RST,
+      output reg [(WIDTH - 1):0] LED
+    );
 
-     )
-     (
-      input [0:0] CLK, 
-    input [0:0] RST, 
-    output reg [(WIDTH - 1):0] LED
-
-     );
       reg [(32 - 1):0] count;
-      always @(posedge CLK)
-      begin        
-      if(RST) begin        
-      count <= 0;
-    end  
-    else begin        
-      if((count == 1023)) begin        
-      count <= 0;
-    end  
-    else begin        
-      count <= (count + 1);
-    end 
-    end 
-    end 
-      always @(posedge CLK)
-      begin        
-      if(RST) begin        
-      LED <= 0;
-    end  
-    else begin        
-      if((count == 1023)) begin        
-      LED <= (LED + 1);
-    end  
-
-    end 
-    end 
+
+      always @(posedge CLK) begin
+        if(RST) begin
+          count <= 0;
+        end else begin
+          if((count == 1023)) begin
+            count <= 0;
+          end else begin
+            count <= (count + 1);
+          end
+        end
+      end
+
+
+      always @(posedge CLK) begin
+        if(RST) begin
+          LED <= 0;
+        end else begin
+          if((count == 1023)) begin
+            LED <= (LED + 1);
+          end 
+        end
+      end
+
+
     endmodule
 
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