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1 parent 8fee1dd commit 3a32d27Copy full SHA for 3a32d27
veriloggen/thread/operator.py
@@ -47,15 +47,15 @@ def getVeriloggenOp(op):
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ast.Add: '__add__',
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ast.Sub: '__sub__',
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ast.Mult: '__mul__',
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- ast.Div: '__div__',
+ ast.Div: '__truediv__',
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ast.Mod: '__mod__',
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ast.Pow: '__pow__',
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ast.LShift: '__lshift__',
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ast.RShift: '__rshift__',
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ast.BitOr: '__or__',
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ast.BitXor: '__xor__',
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ast.BitAnd: '__and__',
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- ast.FloorDiv: '__truediv__',
+ ast.FloorDiv: '__div__',
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ast.And: None,
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ast.Or: None,
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ast.Invert: '__invert__',
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