Merge branch 'feature_simplify_stream' into develop

Author: shtaxxx

examples/fifo_rtl/test_fifo_rtl.py

@@ -81,7 +81,7 @@
   reg [32-1:0] sum;
   reg [32-1:0] fsm;
   localparam fsm_init = 0;
-  assign myfifo_wdata = (fsm == 1)? count : 0;
+  assign myfifo_wdata = (fsm == 1)? count : 'hx;
   assign myfifo_enq = (fsm == 1)? (fsm == 1) && !myfifo_almost_full : 0;
   localparam _tmp_0 = 1;
   wire [_tmp_0-1:0] _tmp_1;

examples/ram_rtl/test_ram_rtl.py

@@ -74,10 +74,10 @@
   reg [32-1:0] addr;
   reg [32-1:0] fsm;
   localparam fsm_init = 0;
-  assign myram_0_wdata = (fsm == 1)? count : 0;
+  assign myram_0_wdata = (fsm == 1)? count : 'hx;
   assign myram_0_wenable = (fsm == 1)? 1'd1 : 0;
   assign myram_0_addr = (fsm == 2)? addr : 
-                        (fsm == 1)? addr : 0;
+                        (fsm == 1)? addr : 'hx;
   assign myram_0_enable = (fsm == 2)? 1'd1 : 
                           (fsm == 1)? 1'd1 : 0;
   localparam _tmp_0 = 1;

examples/simulation_verilator/test_simulation_verilator.py

@@ -711,7 +711,7 @@
   reg [10-1:0] _tmp_5;
   reg [32-1:0] _tmp_6;
   reg _tmp_7;
-  assign ram_a_0_wdata = (_tmp_7)? _tmp_6 : 0;
+  assign ram_a_0_wdata = (_tmp_7)? _tmp_6 : 'hx;
   assign ram_a_0_wenable = (_tmp_7)? 1'd1 : 0;
   reg _ram_a_cond_0_1;
   reg [9-1:0] _tmp_8;
@@ -742,14 +742,14 @@
   reg [10-1:0] _tmp_15;
   reg [32-1:0] _tmp_16;
   reg _tmp_17;
-  assign ram_b_0_wdata = (_tmp_17)? _tmp_16 : 0;
+  assign ram_b_0_wdata = (_tmp_17)? _tmp_16 : 'hx;
   assign ram_b_0_wenable = (_tmp_17)? 1'd1 : 0;
   reg _ram_b_cond_0_1;
   reg __myaxi_read_fsm_cond_3_2_1;
   reg signed [32-1:0] _th_matmul_sum_14;
   reg signed [32-1:0] _th_matmul_k_15;
   assign ram_a_0_addr = (th_matmul == 20)? _th_matmul_k_15 : 
-                        (_tmp_7)? _tmp_5 : 0;
+                        (_tmp_7)? _tmp_5 : 'hx;
   assign ram_a_0_enable = (th_matmul == 20)? 1'd1 : 
                           (_tmp_7)? 1'd1 : 0;
   localparam _tmp_18 = 1;
@@ -759,7 +759,7 @@
   reg signed [32-1:0] _tmp_20;
   reg signed [32-1:0] _th_matmul_x_16;
   assign ram_b_0_addr = (th_matmul == 22)? _th_matmul_k_15 : 
-                        (_tmp_17)? _tmp_15 : 0;
+                        (_tmp_17)? _tmp_15 : 'hx;
   assign ram_b_0_enable = (th_matmul == 22)? 1'd1 : 
                           (_tmp_17)? 1'd1 : 0;
   localparam _tmp_21 = 1;
@@ -835,7 +835,7 @@
   reg [32-1:0] _tmp_45;
   reg _tmp_46;
   assign ram_c_0_wdata = (_tmp_46)? _tmp_45 : 
-                         (th_matmul == 26)? _th_matmul_sum_14 : 0;
+                         (th_matmul == 26)? _th_matmul_sum_14 : 'hx;
   assign ram_c_0_wenable = (_tmp_46)? 1'd1 : 
                            (th_matmul == 26)? 1'd1 : 0;
   reg _ram_c_cond_0_1;
@@ -844,7 +844,7 @@
   assign ram_c_0_addr = (th_matmul == 50)? _th_matmul_j_27 : 
                         (_tmp_46)? _tmp_44 : 
                         (_tmp_30)? _tmp_35 : 
-                        (th_matmul == 26)? _th_matmul_j_13 : 0;
+                        (th_matmul == 26)? _th_matmul_j_13 : 'hx;
   assign ram_c_0_enable = (th_matmul == 50)? 1'd1 : 
                           (_tmp_46)? 1'd1 : 
                           ((_tmp_27 || !_tmp_25) && (_tmp_28 || !_tmp_26) && _tmp_30)? 1'd1 : 

examples/thread_embedded_verilog_ipxact/test_thread_embedded_verilog_ipxact.py

@@ -1355,7 +1355,7 @@
   reg [10-1:0] _tmp_14;
   reg [32-1:0] _tmp_15;
   reg _tmp_16;
-  assign ram_a_0_wdata = (_tmp_16)? _tmp_15 : 0;
+  assign ram_a_0_wdata = (_tmp_16)? _tmp_15 : 'hx;
   assign ram_a_0_wenable = (_tmp_16)? 1'd1 : 0;
   reg _ram_a_cond_0_1;
   reg [9-1:0] _tmp_17;
@@ -1392,7 +1392,7 @@
   reg [33-1:0] _tmp_29;
   reg [10-1:0] _tmp_30;
   assign ram_a_0_addr = (_tmp_25)? _tmp_30 : 
-                        (_tmp_16)? _tmp_14 : 0;
+                        (_tmp_16)? _tmp_14 : 'hx;
   assign ram_a_0_enable = ((_tmp_22 || !_tmp_20) && (_tmp_23 || !_tmp_21) && _tmp_25)? 1'd1 : 
                           (_tmp_16)? 1'd1 : 0;
   reg [9-1:0] _tmp_31;

examples/thread_memcpy_ipxact/test_thread_memcpy_ipxact.py

@@ -1338,7 +1338,7 @@
   reg [10-1:0] _tmp_14;
   reg [32-1:0] _tmp_15;
   reg _tmp_16;
-  assign ram_a_0_wdata = (_tmp_16)? _tmp_15 : 0;
+  assign ram_a_0_wdata = (_tmp_16)? _tmp_15 : 'hx;
   assign ram_a_0_wenable = (_tmp_16)? 1'd1 : 0;
   reg _ram_a_cond_0_1;
   reg [9-1:0] _tmp_17;
@@ -1375,7 +1375,7 @@
   reg [33-1:0] _tmp_29;
   reg [10-1:0] _tmp_30;
   assign ram_a_0_addr = (_tmp_25)? _tmp_30 : 
-                        (_tmp_16)? _tmp_14 : 0;
+                        (_tmp_16)? _tmp_14 : 'hx;
   assign ram_a_0_enable = ((_tmp_22 || !_tmp_20) && (_tmp_23 || !_tmp_21) && _tmp_25)? 1'd1 : 
                           (_tmp_16)? 1'd1 : 0;
   reg [9-1:0] _tmp_31;

examples/thread_stream_axi_stream_fifo/test_thread_stream_axi_stream_fifo.py

@@ -441,7 +441,7 @@
   reg [10-1:0] _tmp_14;
   reg [32-1:0] _tmp_15;
   reg _tmp_16;
-  assign ram_b_0_wdata = (_tmp_16)? _tmp_15 : 0;
+  assign ram_b_0_wdata = (_tmp_16)? _tmp_15 : 'hx;
   assign ram_b_0_wenable = (_tmp_16)? 1'd1 : 0;
   reg _ram_b_cond_0_1;
   reg [9-1:0] _tmp_17;
@@ -460,7 +460,7 @@
   localparam _axi_in_read_fsm_init = 0;
   reg [33-1:0] _axi_in_read_rest_size;
   assign axi_in_tready = (_axi_in_read_fsm == 1) && !fifo_a_almost_full;
-  assign fifo_a_wdata = (axi_in_tready && axi_in_tvalid && (_axi_in_read_op_sel == 1))? axi_in_tdata : 0;
+  assign fifo_a_wdata = (axi_in_tready && axi_in_tvalid && (_axi_in_read_op_sel == 1))? axi_in_tdata : 'hx;
   assign fifo_a_enq = (axi_in_tready && axi_in_tvalid && (_axi_in_read_op_sel == 1))? axi_in_tready && axi_in_tvalid && (_axi_in_read_op_sel == 1) && !fifo_a_almost_full : 0;
   localparam _tmp_20 = 1;
   wire [_tmp_20-1:0] _tmp_21;
@@ -530,36 +530,36 @@
   reg signed [1-1:0] __delay_data_23__delay_22__delay_21__delay_20____variable_3;
   reg signed [32-1:0] __delay_data_17__delay_16__delay_15__delay_14____variable_1;
   reg signed [1-1:0] __delay_data_24__delay_23__delay_22__delay_21____variable_3;
-  reg signed [32-1:0] _reduceadd_data_5;
-  reg [33-1:0] _reduceadd_count_5;
-  reg _reduceadd_prev_count_max_5;
-  wire _reduceadd_reset_cond_5;
-  assign _reduceadd_reset_cond_5 = __delay_data_24__delay_23__delay_22__delay_21____variable_3 || _reduceadd_prev_count_max_5;
-  wire [33-1:0] _reduceadd_current_count_5;
-  assign _reduceadd_current_count_5 = (_reduceadd_reset_cond_5)? 0 : _reduceadd_count_5;
-  wire signed [32-1:0] _reduceadd_current_data_5;
-  assign _reduceadd_current_data_5 = (_reduceadd_reset_cond_5)? 1'sd0 : _reduceadd_data_5;
-  reg [1-1:0] _pulse_data_7;
-  reg [33-1:0] _pulse_count_7;
-  reg _pulse_prev_count_max_7;
-  wire _pulse_reset_cond_7;
-  assign _pulse_reset_cond_7 = __delay_data_24__delay_23__delay_22__delay_21____variable_3 || _pulse_prev_count_max_7;
-  wire [33-1:0] _pulse_current_count_7;
-  assign _pulse_current_count_7 = (_pulse_reset_cond_7)? 0 : _pulse_count_7;
-  wire [1-1:0] _pulse_current_data_7;
-  assign _pulse_current_data_7 = (_pulse_reset_cond_7)? 1'sd0 : _pulse_data_7;
+  reg signed [32-1:0] _reduceadd_data_4;
+  reg [33-1:0] _reduceadd_count_4;
+  reg _reduceadd_prev_count_max_4;
+  wire _reduceadd_reset_cond_4;
+  assign _reduceadd_reset_cond_4 = __delay_data_24__delay_23__delay_22__delay_21____variable_3 || _reduceadd_prev_count_max_4;
+  wire [33-1:0] _reduceadd_current_count_4;
+  assign _reduceadd_current_count_4 = (_reduceadd_reset_cond_4)? 0 : _reduceadd_count_4;
+  wire signed [32-1:0] _reduceadd_current_data_4;
+  assign _reduceadd_current_data_4 = (_reduceadd_reset_cond_4)? 1'sd0 : _reduceadd_data_4;
+  reg [1-1:0] _pulse_data_6;
+  reg [33-1:0] _pulse_count_6;
+  reg _pulse_prev_count_max_6;
+  wire _pulse_reset_cond_6;
+  assign _pulse_reset_cond_6 = __delay_data_24__delay_23__delay_22__delay_21____variable_3 || _pulse_prev_count_max_6;
+  wire [33-1:0] _pulse_current_count_6;
+  assign _pulse_current_count_6 = (_pulse_reset_cond_6)? 0 : _pulse_count_6;
+  wire [1-1:0] _pulse_current_data_6;
+  assign _pulse_current_data_6 = (_pulse_reset_cond_6)? 1'sd0 : _pulse_data_6;
   wire signed [32-1:0] mystream_reduce_sum_data;
-  assign mystream_reduce_sum_data = _reduceadd_data_5;
+  assign mystream_reduce_sum_data = _reduceadd_data_4;
   wire [1-1:0] mystream_reduce_sum_valid_data;
-  assign mystream_reduce_sum_valid_data = _pulse_data_7;
+  assign mystream_reduce_sum_valid_data = _pulse_data_6;
   wire _set_flag_30;
   assign _set_flag_30 = th_comp == 25;
   assign fifo_a_deq = (_mystream_reduce_stream_oready && _mystream_reduce_a_source_fifo_deq && (_mystream_reduce_a_source_sel == 1) && !fifo_a_empty)? 1 : 0;
   localparam _tmp_31 = 1;
   wire [_tmp_31-1:0] _tmp_32;
   assign _tmp_32 = _mystream_reduce_stream_oready && _mystream_reduce_a_source_fifo_deq && (_mystream_reduce_a_source_sel == 1) && !fifo_a_empty;
   reg [_tmp_31-1:0] __tmp_32_1;
-  assign _mystream_reduce_a_source_fifo_rdata = (_mystream_reduce_a_source_sel == 1)? fifo_a_rdata : 0;
+  assign _mystream_reduce_a_source_fifo_rdata = (_mystream_reduce_a_source_sel == 1)? fifo_a_rdata : 'hx;
   reg signed [32-1:0] __variable_wdata_0;
   assign mystream_reduce_a_data = __variable_wdata_0;
   reg [32-1:0] _mystream_reduce_a_source_fsm_0;
@@ -590,7 +590,7 @@
   reg signed [32-1:0] _tmp_52;
   reg signed [32-1:0] _tmp_53;
   reg signed [32-1:0] _tmp_54;
-  assign fifo_b_wdata = (_mystream_reduce_stream_oready && _mystream_reduce_sum_sink_fifo_enq && (_mystream_reduce_sum_sink_sel == 2))? _mystream_reduce_sum_sink_fifo_wdata : 0;
+  assign fifo_b_wdata = (_mystream_reduce_stream_oready && _mystream_reduce_sum_sink_fifo_enq && (_mystream_reduce_sum_sink_sel == 2))? _mystream_reduce_sum_sink_fifo_wdata : 'hx;
   assign fifo_b_enq = (_mystream_reduce_stream_oready && _mystream_reduce_sum_sink_fifo_enq && (_mystream_reduce_sum_sink_sel == 2))? _mystream_reduce_stream_oready && _mystream_reduce_sum_sink_fifo_enq && (_mystream_reduce_sum_sink_sel == 2) && !fifo_b_almost_full : 0;
   localparam _tmp_55 = 1;
   wire [_tmp_55-1:0] _tmp_56;
@@ -612,22 +612,22 @@
   wire [_tmp_58-1:0] _tmp_59;
   assign _tmp_59 = _mystream_bias_stream_oready && _mystream_bias_x_source_fifo_deq && (_mystream_bias_x_source_sel == 1) && !fifo_b_empty;
   reg [_tmp_58-1:0] __tmp_59_1;
-  assign _mystream_bias_x_source_fifo_rdata = (_mystream_bias_x_source_sel == 1)? fifo_b_rdata : 0;
+  assign _mystream_bias_x_source_fifo_rdata = (_mystream_bias_x_source_sel == 1)? fifo_b_rdata : 'hx;
   reg signed [32-1:0] __variable_wdata_8;
   assign mystream_bias_x_data = __variable_wdata_8;
   reg [32-1:0] _mystream_bias_x_source_fsm_0;
   localparam _mystream_bias_x_source_fsm_0_init = 0;
   wire _set_flag_60;
   assign _set_flag_60 = th_comp == 29;
   assign ram_b_0_addr = (_mystream_bias_stream_oready && _mystream_bias_y_source_ram_renable && (_mystream_bias_y_source_sel == 2))? _mystream_bias_y_source_ram_raddr : 
-                        (_tmp_16)? _tmp_14 : 0;
+                        (_tmp_16)? _tmp_14 : 'hx;
   assign ram_b_0_enable = (_mystream_bias_stream_oready && _mystream_bias_y_source_ram_renable && (_mystream_bias_y_source_sel == 2))? 1'd1 : 
                           (_tmp_16)? 1'd1 : 0;
   localparam _tmp_61 = 1;
   wire [_tmp_61-1:0] _tmp_62;
   assign _tmp_62 = _mystream_bias_stream_oready && _mystream_bias_y_source_ram_renable && (_mystream_bias_y_source_sel == 2);
   reg [_tmp_61-1:0] __tmp_62_1;
-  assign _mystream_bias_y_source_ram_rdata = (_mystream_bias_y_source_sel == 2)? ram_b_0_rdata : 0;
+  assign _mystream_bias_y_source_ram_rdata = (_mystream_bias_y_source_sel == 2)? ram_b_0_rdata : 'hx;
   reg signed [32-1:0] __variable_wdata_9;
   assign mystream_bias_y_data = __variable_wdata_9;
   reg [32-1:0] _mystream_bias_y_source_fsm_1;
@@ -640,7 +640,7 @@
   reg signed [32-1:0] _tmp_67;
   reg signed [32-1:0] _tmp_68;
   reg signed [32-1:0] _tmp_69;
-  assign fifo_c_wdata = (_mystream_bias_stream_oready && _mystream_bias_z_sink_fifo_enq && (_mystream_bias_z_sink_sel == 3))? _mystream_bias_z_sink_fifo_wdata : 0;
+  assign fifo_c_wdata = (_mystream_bias_stream_oready && _mystream_bias_z_sink_fifo_enq && (_mystream_bias_z_sink_sel == 3))? _mystream_bias_z_sink_fifo_wdata : 'hx;
   assign fifo_c_enq = (_mystream_bias_stream_oready && _mystream_bias_z_sink_fifo_enq && (_mystream_bias_z_sink_sel == 3))? _mystream_bias_stream_oready && _mystream_bias_z_sink_fifo_enq && (_mystream_bias_z_sink_sel == 3) && !fifo_c_almost_full : 0;
   localparam _tmp_70 = 1;
   wire [_tmp_70-1:0] _tmp_71;
@@ -1257,12 +1257,12 @@
       __delay_data_23__delay_22__delay_21__delay_20____variable_3 <= 0;
       __delay_data_17__delay_16__delay_15__delay_14____variable_1 <= 0;
       __delay_data_24__delay_23__delay_22__delay_21____variable_3 <= 0;
-      _reduceadd_data_5 <= 1'sd0;
-      _reduceadd_count_5 <= 0;
-      _reduceadd_prev_count_max_5 <= 0;
-      _pulse_data_7 <= 1'sd0;
-      _pulse_count_7 <= 0;
-      _pulse_prev_count_max_7 <= 0;
+      _reduceadd_data_4 <= 1'sd0;
+      _reduceadd_count_4 <= 0;
+      _reduceadd_prev_count_max_4 <= 0;
+      _pulse_data_6 <= 1'sd0;
+      _pulse_count_6 <= 0;
+      _pulse_prev_count_max_6 <= 0;
       _mystream_reduce_a_source_mode <= 4'b0;
       _mystream_reduce_a_source_size <= 0;
       _mystream_reduce_a_source_sel <= 0;
@@ -1419,29 +1419,29 @@
       if(_mystream_reduce_stream_oready) begin
         __delay_data_24__delay_23__delay_22__delay_21____variable_3 <= __delay_data_23__delay_22__delay_21__delay_20____variable_3;
       end 
-      if(__mystream_reduce_stream_ivalid_7 && _mystream_reduce_stream_oready && _reduceadd_reset_cond_5) begin
-        _reduceadd_data_5 <= 1'sd0;
+      if(__mystream_reduce_stream_ivalid_7 && _mystream_reduce_stream_oready && _reduceadd_reset_cond_4) begin
+        _reduceadd_data_4 <= 1'sd0;
       end 
       if(__mystream_reduce_stream_ivalid_7 && _mystream_reduce_stream_oready) begin
-        _reduceadd_data_5 <= _reduceadd_current_data_5 + _times_data_2;
+        _reduceadd_data_4 <= _reduceadd_current_data_4 + _times_data_2;
       end 
       if(__mystream_reduce_stream_ivalid_7 && _mystream_reduce_stream_oready) begin
-        _reduceadd_count_5 <= (_reduceadd_current_count_5 >= __delay_data_17__delay_16__delay_15__delay_14____variable_1 - 1)? 0 : _reduceadd_current_count_5 + 1;
+        _reduceadd_count_4 <= (_reduceadd_current_count_4 >= __delay_data_17__delay_16__delay_15__delay_14____variable_1 - 1)? 0 : _reduceadd_current_count_4 + 1;
       end 
       if(__mystream_reduce_stream_ivalid_7 && _mystream_reduce_stream_oready) begin
-        _reduceadd_prev_count_max_5 <= _reduceadd_current_count_5 >= __delay_data_17__delay_16__delay_15__delay_14____variable_1 - 1;
+        _reduceadd_prev_count_max_4 <= _reduceadd_current_count_4 >= __delay_data_17__delay_16__delay_15__delay_14____variable_1 - 1;
       end 
-      if(__mystream_reduce_stream_ivalid_7 && _mystream_reduce_stream_oready && _pulse_reset_cond_7) begin
-        _pulse_data_7 <= 1'sd0;
+      if(__mystream_reduce_stream_ivalid_7 && _mystream_reduce_stream_oready && _pulse_reset_cond_6) begin
+        _pulse_data_6 <= 1'sd0;
       end 
       if(__mystream_reduce_stream_ivalid_7 && _mystream_reduce_stream_oready) begin
-        _pulse_data_7 <= _pulse_current_count_7 >= __delay_data_17__delay_16__delay_15__delay_14____variable_1 - 1;
+        _pulse_data_6 <= _pulse_current_count_6 >= __delay_data_17__delay_16__delay_15__delay_14____variable_1 - 1;
       end 
       if(__mystream_reduce_stream_ivalid_7 && _mystream_reduce_stream_oready) begin
-        _pulse_count_7 <= (_pulse_current_count_7 >= __delay_data_17__delay_16__delay_15__delay_14____variable_1 - 1)? 0 : _pulse_current_count_7 + 1;
+        _pulse_count_6 <= (_pulse_current_count_6 >= __delay_data_17__delay_16__delay_15__delay_14____variable_1 - 1)? 0 : _pulse_current_count_6 + 1;
       end 
       if(__mystream_reduce_stream_ivalid_7 && _mystream_reduce_stream_oready) begin
-        _pulse_prev_count_max_7 <= _pulse_current_count_7 >= __delay_data_17__delay_16__delay_15__delay_14____variable_1 - 1;
+        _pulse_prev_count_max_6 <= _pulse_current_count_6 >= __delay_data_17__delay_16__delay_15__delay_14____variable_1 - 1;
       end 
       if(_set_flag_30) begin
         _mystream_reduce_a_source_mode <= 4'b1000;

examples/thread_verilog_submodule_ipxact/test_thread_verilog_submodule_ipxact.py

@@ -1384,7 +1384,7 @@
   reg [10-1:0] _tmp_14;
   reg [32-1:0] _tmp_15;
   reg _tmp_16;
-  assign ram_a_0_wdata = (_tmp_16)? _tmp_15 : 0;
+  assign ram_a_0_wdata = (_tmp_16)? _tmp_15 : 'hx;
   assign ram_a_0_wenable = (_tmp_16)? 1'd1 : 0;
   reg _ram_a_cond_0_1;
   reg [9-1:0] _tmp_17;
@@ -1422,7 +1422,7 @@
   reg [33-1:0] _tmp_29;
   reg [10-1:0] _tmp_30;
   assign ram_a_0_addr = (_tmp_25)? _tmp_30 : 
-                        (_tmp_16)? _tmp_14 : 0;
+                        (_tmp_16)? _tmp_14 : 'hx;
   assign ram_a_0_enable = ((_tmp_22 || !_tmp_20) && (_tmp_23 || !_tmp_21) && _tmp_25)? 1'd1 : 
                           (_tmp_16)? 1'd1 : 0;
   reg [9-1:0] _tmp_31;

examples_obsolete/dataflow_stencil/test_dataflow_stencil.py

@@ -342,23 +342,23 @@
   reg [32-1:0] read_addr;
   assign src_ram0_0_wdata = 0;
   assign src_ram0_0_wenable = 0;
-  assign src_ram0_0_addr = (read_fsm == 1)? read_addr : 0;
+  assign src_ram0_0_addr = (read_fsm == 1)? read_addr : 'hx;
   assign src_ram0_0_enable = (read_fsm == 1)? 1'd1 : 0;
   localparam _tmp_1 = 1;
   wire [_tmp_1-1:0] _tmp_2;
   assign _tmp_2 = read_fsm == 1;
   reg [_tmp_1-1:0] __tmp_2_1;
   assign src_ram1_0_wdata = 0;
   assign src_ram1_0_wenable = 0;
-  assign src_ram1_0_addr = (read_fsm == 1)? read_addr : 0;
+  assign src_ram1_0_addr = (read_fsm == 1)? read_addr : 'hx;
   assign src_ram1_0_enable = (read_fsm == 1)? 1'd1 : 0;
   localparam _tmp_3 = 1;
   wire [_tmp_3-1:0] _tmp_4;
   assign _tmp_4 = read_fsm == 1;
   reg [_tmp_3-1:0] __tmp_4_1;
   assign src_ram2_0_wdata = 0;
   assign src_ram2_0_wenable = 0;
-  assign src_ram2_0_addr = (read_fsm == 1)? read_addr : 0;
+  assign src_ram2_0_addr = (read_fsm == 1)? read_addr : 'hx;
   assign src_ram2_0_enable = (read_fsm == 1)? 1'd1 : 0;
   localparam _tmp_5 = 1;
   wire [_tmp_5-1:0] _tmp_6;
@@ -431,8 +431,8 @@
   localparam write_fsm_init = 0;
   reg [32-1:0] write_count;
   reg [32-1:0] write_addr;
-  assign dst_ram_0_addr = ((write_fsm == 0) && (ovalid && (write_count > 1)))? write_addr : 0;
-  assign dst_ram_0_wdata = ((write_fsm == 0) && (ovalid && (write_count > 1)))? odata : 0;
+  assign dst_ram_0_addr = ((write_fsm == 0) && (ovalid && (write_count > 1)))? write_addr : 'hx;
+  assign dst_ram_0_wdata = ((write_fsm == 0) && (ovalid && (write_count > 1)))? odata : 'hx;
   assign dst_ram_0_wenable = ((write_fsm == 0) && (ovalid && (write_count > 1)))? 1'd1 : 0;
   assign dst_ram_0_enable = ((write_fsm == 0) && (ovalid && (write_count > 1)))? 1'd1 : 0;