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Merge branch 'develop' into 2.1.0-rc
2 parents bf82fa3 + 7f9fe9c commit 2f962b1

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38 files changed

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-2702
lines changed

‎examples/simulation_verilator/test_simulation_verilator.py‎

Lines changed: 314 additions & 282 deletions
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‎examples/stream_axi_stream_fifo_ipxact_ultra96v2_pynq/test_stream_axi_stream_fifo_ipxact.py‎

Lines changed: 448 additions & 430 deletions
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‎examples/stream_axi_stream_fifo_ultra96v2_pynq/test_stream_axi_stream_fifo.py‎

Lines changed: 448 additions & 430 deletions
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‎examples/thread_embedded_verilog_ipxact/test_thread_embedded_verilog_ipxact.py‎

Lines changed: 302 additions & 274 deletions
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‎examples/thread_memcpy_ipxact_ultra96v2_pynq/test_thread_memcpy_ipxact.py‎

Lines changed: 302 additions & 274 deletions
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‎examples/thread_verilog_submodule_ipxact/test_thread_verilog_submodule_ipxact.py‎

Lines changed: 302 additions & 274 deletions
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‎tests/extension/thread_/axi_dma_multiram/thread_axi_dma_multiram.py‎

Lines changed: 8 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -53,9 +53,6 @@ def blink(size):
5353
def body(size, offset):
5454
# narrow dma test
5555
myaxi.dma_read(myram0, 0, 0, size)
56-
57-
### ???
58-
5956
myaxi.dma_read(myram1, 0, 0, size)
6057
myaxi.dma_read(myram2, 0, 0, size)
6158
myaxi.dma_read(myram3, 0, 0, size)
@@ -83,8 +80,8 @@ def body(size, offset):
8380

8481
laddr = 0
8582
gaddr = offset
86-
myaxi.dma_write([myram0, myram1, myram2, myram3],
87-
laddr, gaddr, size)
83+
myaxi.dma_write_packed([myram0, myram1, myram2, myram3],
84+
laddr, gaddr, size * 4)
8885
print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
8986

9087
# write
@@ -106,15 +103,15 @@ def body(size, offset):
106103

107104
laddr = 0
108105
gaddr = array_size + offset
109-
myaxi.dma_write([myram0, myram1, myram2, myram3],
110-
laddr, gaddr, size)
106+
myaxi.dma_write_packed([myram0, myram1, myram2, myram3],
107+
laddr, gaddr, size * 4)
111108
print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
112109

113110
# read
114111
laddr = 0
115112
gaddr = offset
116-
myaxi.dma_read([myram0, myram1, myram2, myram3],
117-
laddr, gaddr, size)
113+
myaxi.dma_read_packed([myram0, myram1, myram2, myram3],
114+
laddr, gaddr, size * 4)
118115
print('dma_read: [%d] <- [%d]' % (laddr, gaddr))
119116

120117
for i in range(size):
@@ -148,8 +145,8 @@ def body(size, offset):
148145
# read
149146
laddr = 0
150147
gaddr = array_size + offset
151-
myaxi.dma_read([myram0, myram1, myram2, myram3],
152-
laddr, gaddr, size)
148+
myaxi.dma_read_packed([myram0, myram1, myram2, myram3],
149+
laddr, gaddr, size * 4)
153150
print('dma_read: [%d] <- [%d]' % (laddr, gaddr))
154151

155152
for i in range(size):

‎tests/extension/thread_/multibank_nested_ram_dma/thread_multibank_nested_ram_dma.py‎

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,9 @@ def mkLed(memory_datawidth=128):
2525
numbanks=numbanks)
2626
myram1 = vthread.MultibankRAM(m, 'myram1', clk, rst, datawidth, addrwidth,
2727
numbanks=numbanks)
28-
myram = (myram0, myram1)
28+
29+
#myram = vthread.to_multibank_ram((myram0, myram1), keep_hierarchy=True)
30+
myram = vthread.to_multibank_ram((myram0, myram1))
2931

3032
all_ok = m.TmpReg(initval=0)
3133

@@ -59,7 +61,7 @@ def body(size, offset):
5961

6062
laddr = 0
6163
gaddr = offset
62-
myaxi.dma_write(myram, laddr, gaddr, size)
64+
myaxi.dma_write(myram, laddr, gaddr, size * 2 * numbanks)
6365
print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
6466

6567
# write
@@ -71,13 +73,13 @@ def body(size, offset):
7173

7274
laddr = 0
7375
gaddr = array_size + offset
74-
myaxi.dma_write(myram, laddr, gaddr, size)
76+
myaxi.dma_write(myram, laddr, gaddr, size * 2 * numbanks)
7577
print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
7678

7779
# read
7880
laddr = 0
7981
gaddr = offset
80-
myaxi.dma_read(myram, laddr, gaddr, size)
82+
myaxi.dma_read(myram, laddr, gaddr, size * 2 * numbanks)
8183
print('dma_read: [%d] <- [%d]' % (laddr, gaddr))
8284

8385
for bank in range(numbanks):
@@ -94,7 +96,7 @@ def body(size, offset):
9496
# read
9597
laddr = 0
9698
gaddr = array_size + offset
97-
myaxi.dma_read(myram, laddr, gaddr, size)
99+
myaxi.dma_read(myram, laddr, gaddr, size * 2 * numbanks)
98100
print('dma_read: [%d] <- [%d]' % (laddr, gaddr))
99101

100102
for bank in range(numbanks):

‎tests/extension/thread_/multibank_nested_ram_dma_block/thread_multibank_nested_ram_dma_block.py‎

Lines changed: 5 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,6 @@ def mkLed(memory_datawidth=128):
2323
myaxi = vthread.AXIM(m, 'myaxi', clk, rst, memory_datawidth)
2424

2525
pack_size = memory_datawidth // datawidth
26-
2726
rams = [vthread.MultibankRAM(m, 'myram%d' % i, clk, rst, datawidth, addrwidth,
2827
numbanks=pack_size)
2928
for i in range(numbanks)]
@@ -73,9 +72,7 @@ def body(size, offset):
7372

7473
laddr = 0
7574
gaddr = offset
76-
myram.dma_write_block(myaxi, laddr, gaddr,
77-
size // pack_size,
78-
block_size // pack_size)
75+
myaxi.dma_write_block(myram, laddr, gaddr, size, block_size)
7976
print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
8077

8178
# write
@@ -99,17 +96,13 @@ def body(size, offset):
9996

10097
laddr = 0
10198
gaddr = array_size + offset
102-
myram.dma_write_block(myaxi, laddr, gaddr,
103-
size // pack_size,
104-
block_size // pack_size)
99+
myaxi.dma_write_block(myram, laddr, gaddr, size, block_size)
105100
print('dma_write: [%d] -> [%d]' % (laddr, gaddr))
106101

107102
# read
108103
laddr = 0
109104
gaddr = offset
110-
myram.dma_read_block(myaxi, laddr, gaddr,
111-
size // pack_size,
112-
block_size // pack_size)
105+
myaxi.dma_read_block(myram, laddr, gaddr, size, block_size)
113106
print('dma_read: [%d] <- [%d]' % (laddr, gaddr))
114107

115108
count = 0
@@ -136,8 +129,7 @@ def body(size, offset):
136129
# read
137130
laddr = 0
138131
gaddr = array_size + offset
139-
myram.dma_read_block(myaxi, laddr, gaddr, size //
140-
pack_size, block_size // pack_size)
132+
myaxi.dma_read_block(myram, laddr, gaddr, size, block_size)
141133
print('dma_read: [%d] <- [%d]' % (laddr, gaddr))
142134

143135
count = 0
@@ -187,7 +179,7 @@ def mkTest(memimg_name=None, memory_datawidth=128):
187179
params=m.connect_params(led),
188180
ports=m.connect_ports(led))
189181

190-
#simulation.setup_waveform(m, uut)
182+
# simulation.setup_waveform(m, uut)
191183
simulation.setup_clock(m, clk, hperiod=5)
192184
init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
193185

‎tests/extension/thread_/multibank_ram_dma/test_thread_multibank_ram_dma.py‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3,16 +3,16 @@
33

44
import os
55
import veriloggen
6-
import thread_multibank_ram_dma
6+
import thread_axi_dma
77

88

99
def test(request):
1010
veriloggen.reset()
1111

1212
simtype = request.config.getoption('--sim')
1313

14-
rslt = thread_multibank_ram_dma.run(filename=None, simtype=simtype,
15-
outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
14+
rslt = thread_axi_dma.run(filename=None, simtype=simtype,
15+
outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
1616

1717
verify_rslt = rslt.splitlines()[-1]
1818
assert(verify_rslt == '# verify: PASSED')

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