verilog/simulation.py -> simulation_/simulation.py

shtaxxx · shtaxxx · commit 2e89f1a94c0b · 2016-08-14T10:55:11.000+09:00
diff --git a/veriloggen/__init__.py b/veriloggen/__init__.py
@@ -15,7 +15,7 @@
 
 # Verilog 
 from .verilog import from_verilog
-from .verilog import simulation
+from .simulation_ import simulation
 
 # Extension
 from .seq.seq import Seq, TmpSeq, make_condition
diff --git a/veriloggen/simulation_/Makefile b/veriloggen/simulation_/Makefile
@@ -0,0 +1,3 @@
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd
diff --git a/veriloggen/simulation_/simulation.py b/veriloggen/simulation_/simulation.py

Original file line number	Diff line number	Diff line change
`@@ -0,0 +1,3 @@`
	`1`	`+.PHONY: clean`
	`2`	`+clean:`
	`3`	`+ rm -rf .pyc __pycache__ parsetab.py .cache .out .png .dot tmp.v uut.vcd`