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sample/test/ is updated: Test cases are implemented by using pytest.
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+456
-250
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22 files changed

+456
-250
lines changed

‎sample/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,3 +5,4 @@ all: clean
55
clean:
66
make clean -C bram
77
make clean -C led
8+
make clean -C test

‎sample/bram/bram.py‎

Lines changed: 25 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -73,25 +73,35 @@ def mkTop():
7373
m.Instance(mkBram('my_'), 'inst_bram', params, ports)
7474

7575
fsm = lib.FSM(m, 'fsm')
76-
m.Always(Posedge(clk))(
77-
If(rst)(
78-
bramif.addr(0), bramif.datain(0), bramif.write(0), fsm.next(0)
79-
).Else(
80-
fsm( bramif.addr(0), bramif.datain(0), bramif.write(0), fsm.next() ),
81-
fsm( bramif.datain(bramif.datain + 4), fsm.next() ),
82-
fsm( bramif.write(0), fsm.next() ),
76+
init = fsm.get_index()
77+
fsmbody = []
78+
fsmbody.append(
79+
fsm( bramif.addr(0), bramif.datain(0), bramif.write(0), fsm.next() ))
80+
first = fsm.get_index()
81+
fsmbody.append(
82+
fsm( bramif.datain(bramif.datain + 4), fsm.next() ))
83+
fsmbody.append(
84+
fsm( bramif.write(0), fsm.next() ))
85+
fsmbody.append(
8386
fsm(
8487
If(bramif.addr == 128)(
85-
bramif.addr(0), fsm.next(0)
88+
bramif.addr(0), fsm.goto(init)
8689
).Else(
87-
bramif.addr(bramif.addr + 1), fsm.next(1)
88-
))
89-
))
90+
bramif.addr(bramif.addr + 1), fsm.goto(first)
91+
)))
92+
93+
m.Always(Posedge(clk))(
94+
If(rst)(
95+
bramif.addr(0), bramif.datain(0), bramif.write(0), fsm.init()
96+
).Else(
97+
*fsmbody
98+
))
9099

91100
return m
92101

93102
#-------------------------------------------------------------------------------
94-
top = mkTop()
95-
# top.to_verilog('tmp.v')
96-
verilog = top.to_verilog()
97-
print(verilog)
103+
if __name__ == '__main__':
104+
top = mkTop()
105+
# top.to_verilog(filename='tmp.v')
106+
verilog = top.to_verilog()
107+
print(verilog)

‎sample/led/led.py‎

Lines changed: 5 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -28,51 +28,8 @@ def mkLed():
2828

2929
return m
3030

31-
#-------------------------------------------------------------------------------
32-
led = mkLed()
33-
## if filename is not None: the generated source code is written to the file.
34-
verilog = led.to_verilog(filename='tmp.v')
35-
print(verilog)
36-
37-
#-------------------------------------------------------------------------------
38-
expected_verilog = """
39-
module blinkled #
40-
(
41-
parameter WIDTH = 8
42-
)
43-
(
44-
input CLK,
45-
input RST,
46-
output reg [WIDTH-1:0] LED
47-
);
48-
reg [32-1:0] count;
49-
50-
always @(posedge CLK) begin
51-
if(RST) begin
52-
count <= 0;
53-
end else begin
54-
count <= count + 1;
55-
end
56-
end
57-
always @(posedge CLK) begin
58-
if(RST) begin
59-
LED <= 0;
60-
end else begin
61-
if(count == 1023) begin
62-
LED <= LED + 1;
63-
end
64-
end
65-
end
66-
endmodule
67-
"""
68-
69-
from pyverilog.vparser.parser import VerilogParser
70-
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
71-
parser = VerilogParser()
72-
expected_verilog_ast = parser.parse(expected_verilog)
73-
codegen = ASTCodeGenerator()
74-
expected_verilog_code = codegen.visit(expected_verilog_ast)
75-
76-
import difflib
77-
diff = difflib.unified_diff(verilog.splitlines(), expected_verilog_code.splitlines())
78-
print('\n'.join(list(diff)))
31+
if __name__ == '__main__':
32+
led = mkLed()
33+
# led.to_verilog(filename='tmp.v')
34+
verilog = led.to_verilog()
35+
print(verilog)

‎sample/test/Makefile‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
.PHONY: clean
2+
clean:
3+
make clean -C cat
4+
make clean -C class
5+
make clean -C function
6+
make clean -C lib-fsm
7+
make clean -C slice
8+
9+
.PHONY: test
10+
test:
11+
make test -C cat
12+
make test -C class
13+
make test -C function
14+
make test -C lib-fsm
15+
make test -C slice

‎sample/test/cat/Makefile‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
TARGET=led.py
2+
TEST=test_led.py
23
ARGS=
34

45
PYTHON=python3
@@ -8,12 +9,16 @@ PYTHON=python3
89
#OPT=-m cProfile -o profile.rslt
910

1011
.PHONY: all
11-
all: run
12+
all: test
1213

1314
.PHONY: run
1415
run:
1516
$(PYTHON) $(OPT) $(TARGET) $(ARGS)
1617

18+
.PHONY: test
19+
test:
20+
$(PYTHON) -m pytest -vv $(TEST)
21+
1722
.PHONY: check
1823
check:
1924
$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v

‎sample/test/cat/led.py‎

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ def mkLed():
2020

2121
m.Always(Posedge(clk))(
2222
If(rst)(
23-
led(Int(0b00000001, width=8, base=2))
23+
led( Int(0b00000001, width=8, base=2) )
2424
).Else(
2525
If(count == 1024 - 1)(
2626
led( Cat(led[width-2:0], led[width-1]) )
@@ -29,6 +29,7 @@ def mkLed():
2929

3030
return m
3131

32-
led = mkLed()
33-
verilog = led.to_verilog()
34-
print(verilog)
32+
if __name__ == '__main__':
33+
led_module = mkLed()
34+
led_code = led_module.to_verilog()
35+
print(led_code)

‎sample/test/cat/test_led.py‎

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,51 @@
1+
import led
2+
3+
expected_verilog = """
4+
module blinkled #
5+
(
6+
parameter WIDTH = 8
7+
)
8+
(
9+
input CLK,
10+
input RST,
11+
output reg [WIDTH-1:0] LED
12+
);
13+
reg [32-1:0] count;
14+
15+
always @(posedge CLK)
16+
begin
17+
if(RST) begin
18+
count <= 0;
19+
end
20+
else begin
21+
count <= count + 1;
22+
end
23+
end
24+
25+
always @(posedge CLK)
26+
begin
27+
if(RST) begin
28+
LED <= 8'b1;
29+
end
30+
else begin
31+
if(count == 1023) begin
32+
LED <= {LED[WIDTH-2:0], LED[WIDTH-1]};
33+
end
34+
end
35+
end
36+
37+
endmodule
38+
"""
39+
40+
def test_led():
41+
led_module = led.mkLed()
42+
led_code = led_module.to_verilog()
43+
44+
from pyverilog.vparser.parser import VerilogParser
45+
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
46+
parser = VerilogParser()
47+
expected_ast = parser.parse(expected_verilog)
48+
codegen = ASTCodeGenerator()
49+
expected_code = codegen.visit(expected_ast)
50+
51+
assert(led_code == expected_code)

‎sample/test/class/Makefile‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
TARGET=led.py
2+
TEST=test_led.py
23
ARGS=
34

45
PYTHON=python3
@@ -8,12 +9,16 @@ PYTHON=python3
89
#OPT=-m cProfile -o profile.rslt
910

1011
.PHONY: all
11-
all: run
12+
all: test
1213

1314
.PHONY: run
1415
run:
1516
$(PYTHON) $(OPT) $(TARGET) $(ARGS)
1617

18+
.PHONY: test
19+
test:
20+
$(PYTHON) -m pytest -vv $(TEST)
21+
1722
.PHONY: check
1823
check:
1924
$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v

‎sample/test/class/led.py‎

Lines changed: 4 additions & 55 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
import sys
22
import os
3+
34
from veriloggen import *
45

56
class Led(Module):
@@ -27,59 +28,7 @@ def __init__(self, name='blinkled'):
2728
)
2829
))
2930

30-
#-------------------------------------------------------------------------------
31-
import unittest
32-
33-
expected_verilog = """
34-
module blinkled #
35-
(
36-
parameter WIDTH = 8
37-
)
38-
(
39-
input CLK,
40-
input RST,
41-
output reg [WIDTH-1:0] LED
42-
);
43-
reg [32-1:0] count;
44-
45-
always @(posedge CLK) begin
46-
if(RST) begin
47-
count <= 0;
48-
end else begin
49-
count <= count + 1;
50-
end
51-
end
52-
always @(posedge CLK) begin
53-
if(RST) begin
54-
LED <= 0;
55-
end else begin
56-
if(count == 1023) begin
57-
LED <= LED + 1;
58-
end
59-
end
60-
end
61-
endmodule
62-
"""
63-
64-
class TestLed(unittest.TestCase):
65-
def setUp(self):
66-
pass
67-
68-
def test_sample(self):
69-
from pyverilog.vparser.parser import VerilogParser
70-
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
71-
led = Led()
72-
verilog = led.to_verilog()
73-
parser = VerilogParser()
74-
expected_ast = parser.parse(expected_verilog)
75-
codegen = ASTCodeGenerator()
76-
expected_code = codegen.visit(expected_ast)
77-
self.assertTrue( expected_code == verilog )
78-
79-
#import difflib
80-
#diff = difflib.unified_diff(verilog.splitlines(), expected_code.splitlines())
81-
#print('\n'.join(list(diff)))
82-
#self.assertTrue( len(list(diff)) == 0 )
83-
8431
if __name__ == '__main__':
85-
unittest.main()
32+
led_module = Led()
33+
led_code = led_module.to_verilog()
34+
print(led_code)

‎sample/test/class/test_led.py‎

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,45 @@
1+
import led
2+
3+
expected_verilog = """
4+
module blinkled #
5+
(
6+
parameter WIDTH = 8
7+
)
8+
(
9+
input CLK,
10+
input RST,
11+
output reg [WIDTH-1:0] LED
12+
);
13+
reg [32-1:0] count;
14+
15+
always @(posedge CLK) begin
16+
if(RST) begin
17+
count <= 0;
18+
end else begin
19+
count <= count + 1;
20+
end
21+
end
22+
always @(posedge CLK) begin
23+
if(RST) begin
24+
LED <= 0;
25+
end else begin
26+
if(count == 1023) begin
27+
LED <= LED + 1;
28+
end
29+
end
30+
end
31+
endmodule
32+
"""
33+
34+
def test_led():
35+
led_module = led.Led()
36+
led_code = led_module.to_verilog()
37+
38+
from pyverilog.vparser.parser import VerilogParser
39+
from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
40+
parser = VerilogParser()
41+
expected_ast = parser.parse(expected_verilog)
42+
codegen = ASTCodeGenerator()
43+
expected_code = codegen.visit(expected_ast)
44+
45+
assert(led_code == expected_code)

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