Skip to content

Commit 25c9b1f

Browse files
shtaxxxshtaxxx
committed
New test cases for multi-cycle operators.
1 parent d0ba3bd commit 25c9b1f

18 files changed

+1133
-0
lines changed

‎tests/extension/thread_/stream_div/Makefile‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
2+
ARGS=
3+
4+
PYTHON=python3
5+
#PYTHON=python
6+
#OPT=-m pdb
7+
#OPT=-m cProfile -s time
8+
#OPT=-m cProfile -o profile.rslt
9+
10+
.PHONY: all
11+
all: test
12+
13+
.PHONY: run
14+
run:
15+
$(PYTHON) $(OPT) $(TARGET) $(ARGS)
16+
17+
.PHONY: test
18+
test:
19+
$(PYTHON) -m pytest -vv
20+
21+
.PHONY: check
22+
check:
23+
$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
24+
iverilog -tnull -Wall tmp.v
25+
rm -f tmp.v
26+
27+
.PHONY: clean
28+
clean:
29+
rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

‎tests/extension/thread_/stream_div/test_thread_stream_div.py‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
from __future__ import absolute_import
2+
from __future__ import print_function
3+
4+
import os
5+
import veriloggen
6+
import thread_stream_div
7+
8+
9+
def test(request):
10+
veriloggen.reset()
11+
12+
simtype = request.config.getoption('--sim')
13+
14+
rslt = thread_stream_div.run(filename=None, simtype=simtype,
15+
outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
16+
17+
verify_rslt = rslt.splitlines()[-1]
18+
assert(verify_rslt == '# verify: PASSED')

‎tests/extension/thread_/stream_div/thread_stream_div.py‎

Lines changed: 144 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,144 @@
1+
from __future__ import absolute_import
2+
from __future__ import print_function
3+
import sys
4+
import os
5+
6+
# the next line can be removed after installation
7+
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
8+
os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
9+
10+
from veriloggen import *
11+
import veriloggen.thread as vthread
12+
import veriloggen.types.axi as axi
13+
14+
15+
def mkLed():
16+
m = Module('blinkled')
17+
clk = m.Input('CLK')
18+
rst = m.Input('RST')
19+
20+
datawidth = 32
21+
addrwidth = 10
22+
myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth)
23+
ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth)
24+
ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth)
25+
ram_c = vthread.RAM(m, 'ram_c', clk, rst, datawidth, addrwidth)
26+
27+
strm = vthread.Stream(m, 'mystream', clk, rst)
28+
a = strm.source('a')
29+
b = strm.source('b')
30+
a = a + 10000
31+
c = strm.Div(a, b)
32+
strm.sink(c, 'c')
33+
34+
def comp_stream(size, offset):
35+
strm.set_source('a', ram_a, offset, size)
36+
strm.set_source('b', ram_b, offset, size)
37+
strm.set_sink('c', ram_c, offset, size)
38+
strm.run()
39+
strm.join()
40+
41+
def comp_sequential(size, offset):
42+
sum = 0
43+
for i in range(size):
44+
a = ram_a.read(i + offset)
45+
b = ram_b.read(i + offset)
46+
a += 10000
47+
sum = a // b
48+
ram_c.write(i + offset, sum)
49+
50+
def check(size, offset_stream, offset_seq):
51+
all_ok = True
52+
for i in range(size):
53+
st = ram_c.read(i + offset_stream)
54+
sq = ram_c.read(i + offset_seq)
55+
if vthread.verilog.NotEql(st, sq):
56+
all_ok = False
57+
if all_ok:
58+
print('# verify: PASSED')
59+
else:
60+
print('# verify: FAILED')
61+
62+
def comp(size):
63+
# stream
64+
offset = 0
65+
myaxi.dma_read(ram_a, offset, 0, size)
66+
myaxi.dma_read(ram_b, offset, 512, size)
67+
comp_stream(size, offset)
68+
myaxi.dma_write(ram_c, offset, 1024, size)
69+
70+
# sequential
71+
offset = size
72+
myaxi.dma_read(ram_a, offset, 0, size)
73+
myaxi.dma_read(ram_b, offset, 512, size)
74+
comp_sequential(size, offset)
75+
myaxi.dma_write(ram_c, offset, 1024 * 2, size)
76+
77+
# verification
78+
myaxi.dma_read(ram_c, 0, 1024, size)
79+
myaxi.dma_read(ram_c, offset, 1024 * 2, size)
80+
check(size, 0, offset)
81+
82+
vthread.finish()
83+
84+
th = vthread.Thread(m, 'th_comp', clk, rst, comp)
85+
fsm = th.start(32)
86+
87+
return m
88+
89+
90+
def mkTest(memimg_name=None):
91+
m = Module('test')
92+
93+
# target instance
94+
led = mkLed()
95+
96+
# copy paras and ports
97+
params = m.copy_params(led)
98+
ports = m.copy_sim_ports(led)
99+
100+
clk = ports['CLK']
101+
rst = ports['RST']
102+
103+
memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name)
104+
memory.connect(ports, 'myaxi')
105+
106+
uut = m.Instance(led, 'uut',
107+
params=m.connect_params(led),
108+
ports=m.connect_ports(led))
109+
110+
# simulation.setup_waveform(m, uut)
111+
simulation.setup_clock(m, clk, hperiod=5)
112+
init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
113+
114+
init.add(
115+
Delay(1000000),
116+
Systask('finish'),
117+
)
118+
119+
return m
120+
121+
122+
def run(filename='tmp.v', simtype='iverilog', outputfile=None):
123+
124+
if outputfile is None:
125+
outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
126+
127+
memimg_name = 'memimg_' + outputfile
128+
129+
test = mkTest(memimg_name=memimg_name)
130+
131+
if filename is not None:
132+
test.to_verilog(filename)
133+
134+
sim = simulation.Simulator(test, sim=simtype)
135+
rslt = sim.run(outputfile=outputfile)
136+
lines = rslt.splitlines()
137+
if simtype == 'verilator' and lines[-1].startswith('-'):
138+
rslt = '\n'.join(lines[:-1])
139+
return rslt
140+
141+
142+
if __name__ == '__main__':
143+
rslt = run(filename='tmp.v')
144+
print(rslt)

‎tests/extension/thread_/stream_div_multicycle/Makefile‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
2+
ARGS=
3+
4+
PYTHON=python3
5+
#PYTHON=python
6+
#OPT=-m pdb
7+
#OPT=-m cProfile -s time
8+
#OPT=-m cProfile -o profile.rslt
9+
10+
.PHONY: all
11+
all: test
12+
13+
.PHONY: run
14+
run:
15+
$(PYTHON) $(OPT) $(TARGET) $(ARGS)
16+
17+
.PHONY: test
18+
test:
19+
$(PYTHON) -m pytest -vv
20+
21+
.PHONY: check
22+
check:
23+
$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
24+
iverilog -tnull -Wall tmp.v
25+
rm -f tmp.v
26+
27+
.PHONY: clean
28+
clean:
29+
rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

‎tests/extension/thread_/stream_div_multicycle/test_thread_stream_div_multicycle.py‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
from __future__ import absolute_import
2+
from __future__ import print_function
3+
4+
import os
5+
import veriloggen
6+
import thread_stream_div_multicycle
7+
8+
9+
def test(request):
10+
veriloggen.reset()
11+
12+
simtype = request.config.getoption('--sim')
13+
14+
rslt = thread_stream_div_multicycle.run(filename=None, simtype=simtype,
15+
outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
16+
17+
verify_rslt = rslt.splitlines()[-1]
18+
assert(verify_rslt == '# verify: PASSED')

‎tests/extension/thread_/stream_div_multicycle/thread_stream_div_multicycle.py‎

Lines changed: 150 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,150 @@
1+
from __future__ import absolute_import
2+
from __future__ import print_function
3+
import sys
4+
import os
5+
6+
# the next line can be removed after installation
7+
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
8+
os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
9+
10+
from veriloggen import *
11+
import veriloggen.thread as vthread
12+
import veriloggen.types.axi as axi
13+
14+
15+
def mkLed():
16+
m = Module('blinkled')
17+
clk = m.Input('CLK')
18+
rst = m.Input('RST')
19+
20+
datawidth = 32
21+
addrwidth = 10
22+
myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth)
23+
ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth)
24+
ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth)
25+
ram_c = vthread.RAM(m, 'ram_c', clk, rst, datawidth, addrwidth)
26+
27+
strm = vthread.Stream(m, 'mystream', clk, rst)
28+
a = strm.source('a')
29+
b = strm.source('b')
30+
a = a + 10000
31+
c = strm.DivMultiCycle(a, b)
32+
c = c + a + b
33+
c = c - a - b
34+
strm.sink(c, 'c')
35+
36+
def comp_stream(size, offset):
37+
strm.set_source('a', ram_a, offset, size)
38+
strm.set_source('b', ram_b, offset, size)
39+
strm.set_sink('c', ram_c, offset, size)
40+
strm.run()
41+
strm.join()
42+
43+
def comp_sequential(size, offset):
44+
sum = 0
45+
for i in range(size):
46+
a = ram_a.read(i + offset)
47+
b = ram_b.read(i + offset)
48+
a += 10000
49+
sum = a // b
50+
sum += a
51+
sum += b
52+
sum -= a
53+
sum -= b
54+
ram_c.write(i + offset, sum)
55+
56+
def check(size, offset_stream, offset_seq):
57+
all_ok = True
58+
for i in range(size):
59+
st = ram_c.read(i + offset_stream)
60+
sq = ram_c.read(i + offset_seq)
61+
if vthread.verilog.NotEql(st, sq):
62+
all_ok = False
63+
if all_ok:
64+
print('# verify: PASSED')
65+
else:
66+
print('# verify: FAILED')
67+
68+
def comp(size):
69+
# stream
70+
offset = 0
71+
myaxi.dma_read(ram_a, offset, 0, size)
72+
myaxi.dma_read(ram_b, offset, 512, size)
73+
comp_stream(size, offset)
74+
myaxi.dma_write(ram_c, offset, 1024, size)
75+
76+
# sequential
77+
offset = size
78+
myaxi.dma_read(ram_a, offset, 0, size)
79+
myaxi.dma_read(ram_b, offset, 512, size)
80+
comp_sequential(size, offset)
81+
myaxi.dma_write(ram_c, offset, 1024 * 2, size)
82+
83+
# verification
84+
myaxi.dma_read(ram_c, 0, 1024, size)
85+
myaxi.dma_read(ram_c, offset, 1024 * 2, size)
86+
check(size, 0, offset)
87+
88+
vthread.finish()
89+
90+
th = vthread.Thread(m, 'th_comp', clk, rst, comp)
91+
fsm = th.start(32)
92+
93+
return m
94+
95+
96+
def mkTest(memimg_name=None):
97+
m = Module('test')
98+
99+
# target instance
100+
led = mkLed()
101+
102+
# copy paras and ports
103+
params = m.copy_params(led)
104+
ports = m.copy_sim_ports(led)
105+
106+
clk = ports['CLK']
107+
rst = ports['RST']
108+
109+
memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name)
110+
memory.connect(ports, 'myaxi')
111+
112+
uut = m.Instance(led, 'uut',
113+
params=m.connect_params(led),
114+
ports=m.connect_ports(led))
115+
116+
# simulation.setup_waveform(m, uut)
117+
simulation.setup_clock(m, clk, hperiod=5)
118+
init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
119+
120+
init.add(
121+
Delay(1000000),
122+
Systask('finish'),
123+
)
124+
125+
return m
126+
127+
128+
def run(filename='tmp.v', simtype='iverilog', outputfile=None):
129+
130+
if outputfile is None:
131+
outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
132+
133+
memimg_name = 'memimg_' + outputfile
134+
135+
test = mkTest(memimg_name=memimg_name)
136+
137+
if filename is not None:
138+
test.to_verilog(filename)
139+
140+
sim = simulation.Simulator(test, sim=simtype)
141+
rslt = sim.run(outputfile=outputfile)
142+
lines = rslt.splitlines()
143+
if simtype == 'verilator' and lines[-1].startswith('-'):
144+
rslt = '\n'.join(lines[:-1])
145+
return rslt
146+
147+
148+
if __name__ == '__main__':
149+
rslt = run(filename='tmp.v')
150+
print(rslt)

0 commit comments

Comments
 (0)