types.AxiMaster and AxiLiteMaster use SkidBuffer for write_data and read_data.

Author: shtaxxx

veriloggen/types/axi.py

@@ -15,6 +15,7 @@
 
 from veriloggen.seq.seq import make_condition
 from . import util
+from .skidbuffer import SkidBuffer
 
 
 BURST_FIXED = 0b00
@@ -480,6 +481,7 @@ def connect(self, ports, name):
 
 
 class AxiMasterWriteData(AxiWriteData):
+    _O = util.t_Output
 
     def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
                  id_width=0, user_width=0,
@@ -497,6 +499,39 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
         if self.wuser is not None:
             self.wuser.assign(user_mode)
 
+        # user-side signals before skidbuffer
+        wdata = m.TmpRegLike(self.wdata, prefix='_'.join(['', name, 'wdata', 'sb']))
+        wstrb = m.TmpRegLike(self.wstrb, prefix='_'.join(['', name, 'wstrb', 'sb']))
+        wlast = m.TmpRegLike(self.wlast, prefix='_'.join(['', name, 'wlast', 'sb']))
+        wvalid = m.TmpRegLike(self.wvalid, prefix='_'.join(['', name, 'wvalid', 'sb']))
+        wready = m.TmpWireLike(self.wready, prefix='_'.join(['', name, 'wready', 'sb']))
+
+        # skidbuffer
+        sb = SkidBuffer(m, clk, rst,
+                        wvalid, self.wready, *[wdata, wstrb, wlast],
+                        prefix='_'.join(['', 'sb', name, 'writedata']))
+        wready.assign(sb.ready)
+
+        # AXI-side signals after skidbuffer
+        self.wdata.assign(sb[0])
+        self.wstrb.assign(sb[1])
+        self.wlast.assign(sb[2])
+        self.wvalid.assign(sb.valid)
+
+        # save AXI-side references
+        self.orig_wdata = self.wdata
+        self.orig_wstrb = self.wstrb
+        self.orig_wlast = self.wlast
+        self.orig_wvalid = self.wvalid
+        self.orig_wready = self.wready
+
+        # update references for user-side
+        self.wdata = wdata
+        self.wstrb = wstrb
+        self.wlast = wlast
+        self.wvalid = wvalid
+        self.wready = wready
+
     def disable_write(self):
         ports = [self.wdata(0),
                  self.wstrb(0),
@@ -708,6 +743,35 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
         self.clk = clk
         self.rst = rst
 
+        # user-side signals before skidbuffer
+        rdata = m.TmpWireLike(self.rdata, prefix='_'.join(['', name, 'rdata', 'sb']))
+        rlast = m.TmpWireLike(self.rlast, prefix='_'.join(['', name, 'rlast', 'sb']))
+        rvalid = m.TmpWireLike(self.rvalid, prefix='_'.join(['', name, 'rvalid', 'sb']))
+        rready = m.TmpWireLike(self.rready, prefix='_'.join(['', name, 'rready', 'sb']))
+
+        # skidbuffer
+        sb = SkidBuffer(m, clk, rst,
+                        self.rvalid, rready, *[self.rdata, self.rlast],
+                        prefix='_'.join(['', 'sb', name, 'readdata']))
+        rdata.assign(sb[0])
+        rlast.assign(sb[1])
+        rvalid.assign(sb.valid)
+
+        # AXI-side signals after skidbuffer
+        self.rready.assign(sb.ready)
+
+        # save AXI-side references
+        self.orig_rdata = self.rdata
+        self.orig_rlast = self.rlast
+        self.orig_rvalid = self.rvalid
+        self.orig_rready = self.rready
+
+        # update references for user-side
+        self.rdata = rdata
+        self.rlast = rlast
+        self.rvalid = rvalid
+        self.rready = rready
+
     def disable_read(self):
         self.rready.assign(0)
 
@@ -820,6 +884,7 @@ def connect(self, ports, name):
 
 
 class AxiLiteMasterWriteData(AxiLiteWriteData):
+    _O = util.t_Output
 
     def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
                  itype=None, otype=None):
@@ -831,6 +896,35 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
         self.rst = rst
         self.seq = Seq(m, name + '_wdata', clk, rst)
 
+        # user-side signals before skidbuffer
+        wdata = m.TmpRegLike(self.wdata, prefix='_'.join(['', name, 'wdata', 'sb']))
+        wstrb = m.TmpRegLike(self.wstrb, prefix='_'.join(['', name, 'wstrb', 'sb']))
+        wvalid = m.TmpRegLike(self.wvalid, prefix='_'.join(['', name, 'wvalid', 'sb']))
+        wready = m.TmpWireLike(self.wready, prefix='_'.join(['', name, 'wready', 'sb']))
+
+        # skidbuffer
+        sb = SkidBuffer(m, clk, rst,
+                        wvalid, self.wready, *[wdata, wstrb],
+                        prefix='_'.join(['', 'sb', name, 'writedata']))
+        wready.assign(sb.ready)
+
+        # AXI-side signals after skidbuffer
+        self.wdata.assign(sb[0])
+        self.wstrb.assign(sb[1])
+        self.wvalid.assign(sb.valid)
+
+        # save AXI-side references
+        self.orig_wdata = self.wdata
+        self.orig_wstrb = self.wstrb
+        self.orig_wvalid = self.wvalid
+        self.orig_wready = self.wready
+
+        # update references for user-side
+        self.wdata = wdata
+        self.wstrb = wstrb
+        self.wvalid = wvalid
+        self.wready = wready
+
     def disable_write(self):
         ports = [self.wdata(0),
                  self.wstrb(0),
@@ -980,6 +1074,31 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
         self.clk = clk
         self.rst = rst
 
+        # user-side signals before skidbuffer
+        rdata = m.TmpWireLike(self.rdata, prefix='_'.join(['', name, 'rdata', 'sb']))
+        rvalid = m.TmpWireLike(self.rvalid, prefix='_'.join(['', name, 'rvalid', 'sb']))
+        rready = m.TmpWireLike(self.rready, prefix='_'.join(['', name, 'rready', 'sb']))
+
+        # skidbuffer
+        sb = SkidBuffer(m, clk, rst,
+                        self.rvalid, rready, *[self.rdata],
+                        prefix='_'.join(['', 'sb', name, 'readdata']))
+        rdata.assign(sb[0])
+        rvalid.assign(sb.valid)
+
+        # AXI-side signals after skidbuffer
+        self.rready.assign(sb.ready)
+
+        # save AXI-side references
+        self.orig_rdata = self.rdata
+        self.orig_rvalid = self.rvalid
+        self.orig_rready = self.rready
+
+        # update references for user-side
+        self.rdata = rdata
+        self.rvalid = rvalid
+        self.rready = rready
+
     def disable_read(self):
         self.rready.assign(0)
 
@@ -1152,6 +1271,7 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
 
         itype = util.t_Wire if noio else None
         otype = util.t_Reg if noio else None
+        wdata_otype = util.t_Wire if noio else None
         rdata_otype = util.t_Wire if noio else None
 
         self.waddr = AxiMasterWriteAddress(m, name, clk, rst, datawidth, addrwidth,
@@ -1162,7 +1282,7 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
         self.wdata = AxiMasterWriteData(m, name, clk, rst, datawidth, addrwidth,
                                         wdata_id_width, wdata_user_width,
                                         wdata_user_mode,
-                                        itype, otype)
+                                        itype, wdata_otype)
         self.wresp = AxiMasterWriteResponse(m, name, clk, rst, datawidth, addrwidth,
                                             wresp_id_width, wresp_user_width, itype, otype)
         self.raddr = AxiMasterReadAddress(m, name, clk, rst, datawidth, addrwidth,
@@ -1332,13 +1452,14 @@ def __init__(self, m, name, clk, rst, datawidth=32, addrwidth=32,
 
         itype = util.t_Wire if noio else None
         otype = util.t_Reg if noio else None
+        wdata_otype = util.t_Wire if noio else None
         rdata_otype = util.t_Wire if noio else None
 
         self.waddr = AxiLiteMasterWriteAddress(m, name, clk, rst, datawidth, addrwidth,
                                                waddr_cache_mode, waddr_prot_mode,
                                                itype, otype)
         self.wdata = AxiLiteMasterWriteData(m, name, clk, rst, datawidth, addrwidth,
-                                            itype, otype)
+                                            itype, wdata_otype)
         self.wresp = AxiLiteMasterWriteResponse(m, name, clk, rst, datawidth, addrwidth,
                                                 itype, otype)
         self.raddr = AxiLiteMasterReadAddress(m, name, clk, rst, datawidth, addrwidth,

veriloggen/types/skidbuffer.py

@@ -0,0 +1,111 @@
+from __future__ import absolute_import
+from __future__ import print_function
+
+import veriloggen.core.vtypes as vtypes
+from veriloggen.seq.seq import TmpSeq
+
+
+class SkidBuffer(vtypes.VeriloggenNode):
+
+    def __init__(self, m, clk, rst,
+                 s_valid, m_ready, *s_values, prefix=None):
+
+        if prefix is None:
+            prefix = 'skidbuffer'
+
+        if not s_values:
+            raise ValueError("'s_values' must not be empty.")
+
+        self.m = m
+        self.clk = clk
+        self.rst = rst
+        self.s_values = s_values
+        self.s_valid = s_valid
+        self.m_ready = m_ready
+
+        width = 0
+        for s_value in s_values:
+            w = s_value.get_width()
+            if w is None:
+                w = 1
+            width += w
+
+        s_data = m.TmpWire(width, prefix=prefix + '_data')
+        s_data.assign(vtypes.Cat(*s_values))
+
+        (m_data, m_valid, s_ready) = make_skidbuffer(m, clk, rst,
+                                                     s_data, s_valid, m_ready,
+                                                     prefix=prefix)
+
+        self.m_values = []
+        msb = width - 1
+        for s_value in s_values:
+            v = m.TmpWireLike(s_value, prefix=prefix + '_value')
+            w = v.get_width()
+            if w is None:
+                w = 1
+            lsb = msb - w + 1
+            v.assign(vtypes.Slice(m_data, msb, lsb))
+            self.m_values.append(v)
+            msb -= w
+
+        self.m_valid = m_valid
+        self.s_ready = s_ready
+
+    @property
+    def values(self):
+        return self.m_values
+
+    @property
+    def valid(self):
+        return self.m_valid
+
+    @property
+    def ready(self):
+        return self.s_ready
+
+    def __getitem__(self, index):
+        return self.m_values[index]
+
+
+def make_skidbuffer(m, clk, rst,
+                    s_data, s_valid, m_ready,
+                    prefix=None):
+
+    if prefix is None:
+        if hasattr(s_data, 'name'):
+            prefix = '_'.join([s_data.name, 'skidbuffer'])
+        else:
+            prefix = 'skidbuffer'
+
+    m_data = m.TmpRegLike(s_data, prefix=prefix + '_data')
+    m_valid = m.TmpReg(prefix=prefix + '_valid', initval=0)
+
+    s_ready = m.TmpWire(prefix=prefix + '_ready')
+
+    tmp_data = m.TmpRegLike(s_data, prefix=prefix + '_tmp_data')
+    tmp_valid = m.TmpReg(prefix=prefix + '_tmp_valid', initval=0)
+
+    next_data = m.TmpWireLike(s_data, prefix=prefix + '_next_data')
+    next_valid = m.TmpWire(prefix=prefix + '_next_valid')
+
+    s_ready.assign(vtypes.Not(tmp_valid))
+
+    next_data.assign(vtypes.Mux(tmp_valid, tmp_data, s_data))
+    next_valid.assign(vtypes.Ors(tmp_valid, s_valid))
+
+    seq = TmpSeq(m, clk, rst, prefix=prefix + '_seq')
+
+    seq.If(vtypes.Ors(m_ready, vtypes.Not(m_valid)))(
+        m_data(next_data),
+        m_valid(next_valid),
+    )
+    seq.If(vtypes.Not(tmp_valid), m_valid, vtypes.Not(m_ready))(
+        tmp_data(s_data),
+        tmp_valid(s_valid),
+    )
+    seq.If(tmp_valid, m_ready)(
+        tmp_valid(0)
+    )
+
+    return m_data, m_valid, s_ready