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2 parents f08ed26 + 90d1857 commit 21f31b7Copy full SHA for 21f31b7
veriloggen/thread/ram.py
@@ -361,8 +361,8 @@ def _id(self):
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@property
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def length(self):
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if isinstance(self.addrwidth, int):
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- return (2 ** self.addrwidth) * self.numbanks
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- return (vtypes.Int(2) ** self.addrwidth) * self.numbanks
+ return 2 ** self.addrwidth
+ return vtypes.Int(2) ** self.addrwidth
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def has_enable(self, port):
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for ram in self.rams:
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