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Merge branch 'feature_stream_update' into develop
2 parents 8757668 + fe82996 commit 1865310

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11 files changed

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‎tests/extension/thread_/stream_add_n/Makefile‎

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TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
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ARGS=
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PYTHON=python3
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#PYTHON=python
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#OPT=-m pdb
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#OPT=-m cProfile -s time
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#OPT=-m cProfile -o profile.rslt
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.PHONY: all
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all: test
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.PHONY: run
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run:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS)
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.PHONY: test
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test:
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$(PYTHON) -m pytest -vv
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.PHONY: check
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check:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
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iverilog -tnull -Wall tmp.v
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rm -f tmp.v
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.PHONY: clean
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clean:
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rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

‎tests/extension/thread_/stream_add_n/test_thread_stream_add_n.py‎

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from __future__ import absolute_import
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from __future__ import print_function
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import os
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import veriloggen
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import thread_stream_add_n
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def test(request):
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veriloggen.reset()
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simtype = request.config.getoption('--sim')
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rslt = thread_stream_add_n.run(filename=None, simtype=simtype,
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outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
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verify_rslt = rslt.splitlines()[-1]
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assert(verify_rslt == '# verify: PASSED')

‎tests/extension/thread_/stream_add_n/thread_stream_add_n.py‎

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from __future__ import absolute_import
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from __future__ import print_function
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import sys
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import os
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# the next line can be removed after installation
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sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
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os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
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from veriloggen import *
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import veriloggen.thread as vthread
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import veriloggen.types.axi as axi
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def mkLed():
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m = Module('blinkled')
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clk = m.Input('CLK')
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rst = m.Input('RST')
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datawidth = 32
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addrwidth = 10
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myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth)
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ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth)
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ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth)
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ram_c = vthread.RAM(m, 'ram_c', clk, rst, datawidth, addrwidth)
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strm = vthread.Stream(m, 'mystream', clk, rst)
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a = strm.source('a')
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b = strm.source('b')
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c = strm.AddN(a, b, a, b)
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#c.latency = 8
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c = c - a - b
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strm.sink(c, 'c')
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def comp_stream(size, offset):
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strm.set_source('a', ram_a, offset, size)
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strm.set_source('b', ram_b, offset, size)
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strm.set_sink('c', ram_c, offset, size)
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strm.run()
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strm.join()
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def comp_sequential(size, offset):
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sum = 0
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for i in range(size):
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a = ram_a.read(i + offset)
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b = ram_b.read(i + offset)
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sum = a + b
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ram_c.write(i + offset, sum)
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def check(size, offset_stream, offset_seq):
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all_ok = True
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for i in range(size):
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st = ram_c.read(i + offset_stream)
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sq = ram_c.read(i + offset_seq)
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if vthread.verilog.NotEql(st, sq):
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all_ok = False
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if all_ok:
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print('# verify: PASSED')
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else:
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print('# verify: FAILED')
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def comp(size):
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# stream
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offset = 0
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myaxi.dma_read(ram_a, offset, 0, size)
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myaxi.dma_read(ram_b, offset, 512, size)
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comp_stream(size, offset)
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myaxi.dma_write(ram_c, offset, 1024, size)
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# sequential
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offset = size
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myaxi.dma_read(ram_a, offset, 0, size)
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myaxi.dma_read(ram_b, offset, 512, size)
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comp_sequential(size, offset)
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myaxi.dma_write(ram_c, offset, 1024 * 2, size)
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# verification
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check(size, 0, offset)
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vthread.finish()
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th = vthread.Thread(m, 'th_comp', clk, rst, comp)
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fsm = th.start(32)
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return m
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def mkTest(memimg_name=None):
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m = Module('test')
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# target instance
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led = mkLed()
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# copy paras and ports
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params = m.copy_params(led)
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ports = m.copy_sim_ports(led)
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clk = ports['CLK']
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rst = ports['RST']
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memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name)
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memory.connect(ports, 'myaxi')
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uut = m.Instance(led, 'uut',
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params=m.connect_params(led),
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ports=m.connect_ports(led))
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#simulation.setup_waveform(m, uut)
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simulation.setup_clock(m, clk, hperiod=5)
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init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
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init.add(
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Delay(1000000),
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Systask('finish'),
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)
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return m
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def run(filename='tmp.v', simtype='iverilog', outputfile=None):
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if outputfile is None:
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outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
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memimg_name = 'memimg_' + outputfile
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test = mkTest(memimg_name=memimg_name)
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if filename is not None:
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test.to_verilog(filename)
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sim = simulation.Simulator(test, sim=simtype)
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rslt = sim.run(outputfile=outputfile)
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lines = rslt.splitlines()
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if simtype == 'verilator' and lines[-1].startswith('-'):
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rslt = '\n'.join(lines[:-1])
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return rslt
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if __name__ == '__main__':
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rslt = run(filename='tmp.v')
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print(rslt)

‎tests/extension/thread_/stream_muladd/Makefile‎

Lines changed: 29 additions & 0 deletions
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TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
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ARGS=
3+
4+
PYTHON=python3
5+
#PYTHON=python
6+
#OPT=-m pdb
7+
#OPT=-m cProfile -s time
8+
#OPT=-m cProfile -o profile.rslt
9+
10+
.PHONY: all
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all: test
12+
13+
.PHONY: run
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run:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS)
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.PHONY: test
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test:
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$(PYTHON) -m pytest -vv
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.PHONY: check
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check:
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$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
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iverilog -tnull -Wall tmp.v
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rm -f tmp.v
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.PHONY: clean
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clean:
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rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

‎tests/extension/thread_/stream_muladd/test_thread_stream_muladd.py‎

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from __future__ import absolute_import
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from __future__ import print_function
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import os
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import veriloggen
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import thread_stream_muladd
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def test(request):
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veriloggen.reset()
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simtype = request.config.getoption('--sim')
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rslt = thread_stream_muladd.run(filename=None, simtype=simtype,
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outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
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verify_rslt = rslt.splitlines()[-1]
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assert(verify_rslt == '# verify: PASSED')

‎tests/extension/thread_/stream_muladd/thread_stream_muladd.py‎

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from __future__ import absolute_import
2+
from __future__ import print_function
3+
import sys
4+
import os
5+
6+
# the next line can be removed after installation
7+
sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
8+
os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
9+
10+
from veriloggen import *
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import veriloggen.thread as vthread
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import veriloggen.types.axi as axi
13+
14+
15+
def mkLed():
16+
m = Module('blinkled')
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clk = m.Input('CLK')
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rst = m.Input('RST')
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datawidth = 32
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addrwidth = 10
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myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth)
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ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth)
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ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth)
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ram_c = vthread.RAM(m, 'ram_c', clk, rst, datawidth, addrwidth)
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strm = vthread.Stream(m, 'mystream', clk, rst)
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a = strm.source('a')
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b = strm.source('b')
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c = strm.MulAdd(a, b, b)
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strm.sink(c, 'c')
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def comp_stream(size, offset):
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strm.set_source('a', ram_a, offset, size)
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strm.set_source('b', ram_b, offset, size)
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strm.set_sink('c', ram_c, offset, size)
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strm.run()
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strm.join()
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def comp_sequential(size, offset):
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sum = 0
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for i in range(size):
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a = ram_a.read(i + offset)
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b = ram_b.read(i + offset)
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sum = a * b + b
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ram_c.write(i + offset, sum)
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def check(size, offset_stream, offset_seq):
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all_ok = True
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for i in range(size):
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st = ram_c.read(i + offset_stream)
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sq = ram_c.read(i + offset_seq)
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if vthread.verilog.NotEql(st, sq):
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all_ok = False
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if all_ok:
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print('# verify: PASSED')
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else:
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print('# verify: FAILED')
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def comp(size):
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# stream
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offset = 0
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myaxi.dma_read(ram_a, offset, 0, size)
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myaxi.dma_read(ram_b, offset, 512, size)
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comp_stream(size, offset)
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myaxi.dma_write(ram_c, offset, 1024, size)
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# sequential
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offset = size
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myaxi.dma_read(ram_a, offset, 0, size)
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myaxi.dma_read(ram_b, offset, 512, size)
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comp_sequential(size, offset)
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myaxi.dma_write(ram_c, offset, 1024 * 2, size)
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# verification
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check(size, 0, offset)
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vthread.finish()
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th = vthread.Thread(m, 'th_comp', clk, rst, comp)
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fsm = th.start(32)
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return m
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def mkTest(memimg_name=None):
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m = Module('test')
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# target instance
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led = mkLed()
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# copy paras and ports
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params = m.copy_params(led)
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ports = m.copy_sim_ports(led)
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clk = ports['CLK']
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rst = ports['RST']
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memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name)
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memory.connect(ports, 'myaxi')
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uut = m.Instance(led, 'uut',
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params=m.connect_params(led),
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ports=m.connect_ports(led))
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#simulation.setup_waveform(m, uut)
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simulation.setup_clock(m, clk, hperiod=5)
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init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
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init.add(
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Delay(1000000),
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Systask('finish'),
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)
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return m
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def run(filename='tmp.v', simtype='iverilog', outputfile=None):
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if outputfile is None:
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outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
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memimg_name = 'memimg_' + outputfile
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test = mkTest(memimg_name=memimg_name)
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if filename is not None:
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test.to_verilog(filename)
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sim = simulation.Simulator(test, sim=simtype)
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rslt = sim.run(outputfile=outputfile)
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lines = rslt.splitlines()
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if simtype == 'verilator' and lines[-1].startswith('-'):
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rslt = '\n'.join(lines[:-1])
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return rslt
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if __name__ == '__main__':
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rslt = run(filename='tmp.v')
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print(rslt)

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