Merge branch 'fix_axi_axuser_width' into develop

Author: shtaxxx

examples/simulation_verilator/test_simulation_verilator.py

@@ -22,7 +22,7 @@
   wire [4-1:0] myaxi_awcache;
   wire [3-1:0] myaxi_awprot;
   wire [4-1:0] myaxi_awqos;
-  wire [1-1:0] myaxi_awuser;
+  wire [2-1:0] myaxi_awuser;
   wire myaxi_awvalid;
   reg myaxi_awready;
   wire [32-1:0] myaxi_wdata;
@@ -41,7 +41,7 @@
   wire [4-1:0] myaxi_arcache;
   wire [3-1:0] myaxi_arprot;
   wire [4-1:0] myaxi_arqos;
-  wire [1-1:0] myaxi_aruser;
+  wire [2-1:0] myaxi_aruser;
   wire myaxi_arvalid;
   reg myaxi_arready;
   reg [32-1:0] myaxi_rdata;
@@ -57,7 +57,7 @@
   wire [4-1:0] memory_awcache;
   wire [3-1:0] memory_awprot;
   wire [4-1:0] memory_awqos;
-  wire [1-1:0] memory_awuser;
+  wire [2-1:0] memory_awuser;
   wire memory_awvalid;
   reg memory_awready;
   wire [32-1:0] memory_wdata;
@@ -76,7 +76,7 @@
   wire [4-1:0] memory_arcache;
   wire [3-1:0] memory_arprot;
   wire [4-1:0] memory_arqos;
-  wire [1-1:0] memory_aruser;
+  wire [2-1:0] memory_aruser;
   wire memory_arvalid;
   reg memory_arready;
   reg [32-1:0] memory_rdata;
@@ -550,7 +550,7 @@
   output [4-1:0] myaxi_awcache,
   output [3-1:0] myaxi_awprot,
   output [4-1:0] myaxi_awqos,
-  output [1-1:0] myaxi_awuser,
+  output [2-1:0] myaxi_awuser,
   output reg myaxi_awvalid,
   input myaxi_awready,
   output reg [32-1:0] myaxi_wdata,
@@ -569,7 +569,7 @@
   output [4-1:0] myaxi_arcache,
   output [3-1:0] myaxi_arprot,
   output [4-1:0] myaxi_arqos,
-  output [1-1:0] myaxi_aruser,
+  output [2-1:0] myaxi_aruser,
   output reg myaxi_arvalid,
   input myaxi_arready,
   input [32-1:0] myaxi_rdata,

examples/thread_embedded_verilog_ipcore/test_thread_embedded_verilog_ipxact.py

@@ -17,7 +17,7 @@
   wire [4-1:0] uut_maxi_awcache;
   wire [3-1:0] uut_maxi_awprot;
   wire [4-1:0] uut_maxi_awqos;
-  wire [1-1:0] uut_maxi_awuser;
+  wire [2-1:0] uut_maxi_awuser;
   wire uut_maxi_awvalid;
   reg uut_maxi_awready;
   wire [32-1:0] uut_maxi_wdata;
@@ -36,7 +36,7 @@
   wire [4-1:0] uut_maxi_arcache;
   wire [3-1:0] uut_maxi_arprot;
   wire [4-1:0] uut_maxi_arqos;
-  wire [1-1:0] uut_maxi_aruser;
+  wire [2-1:0] uut_maxi_aruser;
   wire uut_maxi_arvalid;
   reg uut_maxi_arready;
   reg [32-1:0] uut_maxi_rdata;
@@ -138,7 +138,7 @@
   wire [4-1:0] memory_awcache;
   wire [3-1:0] memory_awprot;
   wire [4-1:0] memory_awqos;
-  wire [1-1:0] memory_awuser;
+  wire [2-1:0] memory_awuser;
   wire memory_awvalid;
   reg memory_awready;
   wire [32-1:0] memory_wdata;
@@ -157,7 +157,7 @@
   wire [4-1:0] memory_arcache;
   wire [3-1:0] memory_arprot;
   wire [4-1:0] memory_arqos;
-  wire [1-1:0] memory_aruser;
+  wire [2-1:0] memory_aruser;
   wire memory_arvalid;
   reg memory_arready;
   reg [32-1:0] memory_rdata;
@@ -1127,7 +1127,7 @@
   output [4-1:0] maxi_awcache,
   output [3-1:0] maxi_awprot,
   output [4-1:0] maxi_awqos,
-  output [1-1:0] maxi_awuser,
+  output [2-1:0] maxi_awuser,
   output reg maxi_awvalid,
   input maxi_awready,
   output reg [32-1:0] maxi_wdata,
@@ -1146,7 +1146,7 @@
   output [4-1:0] maxi_arcache,
   output [3-1:0] maxi_arprot,
   output [4-1:0] maxi_arqos,
-  output [1-1:0] maxi_aruser,
+  output [2-1:0] maxi_aruser,
   output reg maxi_arvalid,
   input maxi_arready,
   input [32-1:0] maxi_rdata,

examples/thread_memcpy_ipxact/test_thread_memcpy_ipxact.py

@@ -16,7 +16,7 @@
   wire [4-1:0] uut_maxi_awcache;
   wire [3-1:0] uut_maxi_awprot;
   wire [4-1:0] uut_maxi_awqos;
-  wire [1-1:0] uut_maxi_awuser;
+  wire [2-1:0] uut_maxi_awuser;
   wire uut_maxi_awvalid;
   reg uut_maxi_awready;
   wire [32-1:0] uut_maxi_wdata;
@@ -35,7 +35,7 @@
   wire [4-1:0] uut_maxi_arcache;
   wire [3-1:0] uut_maxi_arprot;
   wire [4-1:0] uut_maxi_arqos;
-  wire [1-1:0] uut_maxi_aruser;
+  wire [2-1:0] uut_maxi_aruser;
   wire uut_maxi_arvalid;
   reg uut_maxi_arready;
   reg [32-1:0] uut_maxi_rdata;
@@ -136,7 +136,7 @@
   wire [4-1:0] memory_awcache;
   wire [3-1:0] memory_awprot;
   wire [4-1:0] memory_awqos;
-  wire [1-1:0] memory_awuser;
+  wire [2-1:0] memory_awuser;
   wire memory_awvalid;
   reg memory_awready;
   wire [32-1:0] memory_wdata;
@@ -155,7 +155,7 @@
   wire [4-1:0] memory_arcache;
   wire [3-1:0] memory_arprot;
   wire [4-1:0] memory_arqos;
-  wire [1-1:0] memory_aruser;
+  wire [2-1:0] memory_aruser;
   wire memory_arvalid;
   reg memory_arready;
   reg [32-1:0] memory_rdata;
@@ -1124,7 +1124,7 @@
   output [4-1:0] maxi_awcache,
   output [3-1:0] maxi_awprot,
   output [4-1:0] maxi_awqos,
-  output [1-1:0] maxi_awuser,
+  output [2-1:0] maxi_awuser,
   output reg maxi_awvalid,
   input maxi_awready,
   output reg [32-1:0] maxi_wdata,
@@ -1143,7 +1143,7 @@
   output [4-1:0] maxi_arcache,
   output [3-1:0] maxi_arprot,
   output [4-1:0] maxi_arqos,
-  output [1-1:0] maxi_aruser,
+  output [2-1:0] maxi_aruser,
   output reg maxi_arvalid,
   input maxi_arready,
   input [32-1:0] maxi_rdata,

examples/thread_verilog_submodule_ipxact/test_thread_verilog_submodule_ipxact.py

@@ -17,7 +17,7 @@
   wire [4-1:0] uut_maxi_awcache;
   wire [3-1:0] uut_maxi_awprot;
   wire [4-1:0] uut_maxi_awqos;
-  wire [1-1:0] uut_maxi_awuser;
+  wire [2-1:0] uut_maxi_awuser;
   wire uut_maxi_awvalid;
   reg uut_maxi_awready;
   wire [32-1:0] uut_maxi_wdata;
@@ -36,7 +36,7 @@
   wire [4-1:0] uut_maxi_arcache;
   wire [3-1:0] uut_maxi_arprot;
   wire [4-1:0] uut_maxi_arqos;
-  wire [1-1:0] uut_maxi_aruser;
+  wire [2-1:0] uut_maxi_aruser;
   wire uut_maxi_arvalid;
   reg uut_maxi_arready;
   reg [32-1:0] uut_maxi_rdata;
@@ -138,7 +138,7 @@
   wire [4-1:0] memory_awcache;
   wire [3-1:0] memory_awprot;
   wire [4-1:0] memory_awqos;
-  wire [1-1:0] memory_awuser;
+  wire [2-1:0] memory_awuser;
   wire memory_awvalid;
   reg memory_awready;
   wire [32-1:0] memory_wdata;
@@ -157,7 +157,7 @@
   wire [4-1:0] memory_arcache;
   wire [3-1:0] memory_arprot;
   wire [4-1:0] memory_arqos;
-  wire [1-1:0] memory_aruser;
+  wire [2-1:0] memory_aruser;
   wire memory_arvalid;
   reg memory_arready;
   reg [32-1:0] memory_rdata;
@@ -1127,7 +1127,7 @@
   output [4-1:0] maxi_awcache,
   output [3-1:0] maxi_awprot,
   output [4-1:0] maxi_awqos,
-  output [1-1:0] maxi_awuser,
+  output [2-1:0] maxi_awuser,
   output reg maxi_awvalid,
   input maxi_awready,
   output reg [32-1:0] maxi_wdata,
@@ -1146,7 +1146,7 @@
   output [4-1:0] maxi_arcache,
   output [3-1:0] maxi_arprot,
   output [4-1:0] maxi_arqos,
-  output [1-1:0] maxi_aruser,
+  output [2-1:0] maxi_aruser,
   output reg maxi_arvalid,
   input maxi_arready,
   input [32-1:0] maxi_rdata,

tests/extension/types_/axi_/axi_to_ram/test_types_axi_axi_to_ram.py

@@ -16,7 +16,7 @@
   wire [4-1:0] myaxi_awcache;
   wire [3-1:0] myaxi_awprot;
   wire [4-1:0] myaxi_awqos;
-  wire [1-1:0] myaxi_awuser;
+  wire [2-1:0] myaxi_awuser;
   wire myaxi_awvalid;
   reg myaxi_awready;
   wire [32-1:0] myaxi_wdata;
@@ -35,7 +35,7 @@
   wire [4-1:0] myaxi_arcache;
   wire [3-1:0] myaxi_arprot;
   wire [4-1:0] myaxi_arqos;
-  wire [1-1:0] myaxi_aruser;
+  wire [2-1:0] myaxi_aruser;
   wire myaxi_arvalid;
   reg myaxi_arready;
   reg [32-1:0] myaxi_rdata;
@@ -249,7 +249,7 @@
   output [4-1:0] myaxi_awcache,
   output [3-1:0] myaxi_awprot,
   output [4-1:0] myaxi_awqos,
-  output [1-1:0] myaxi_awuser,
+  output [2-1:0] myaxi_awuser,
   output reg myaxi_awvalid,
   input myaxi_awready,
   output reg [32-1:0] myaxi_wdata,
@@ -268,7 +268,7 @@
   output [4-1:0] myaxi_arcache,
   output [3-1:0] myaxi_arprot,
   output [4-1:0] myaxi_arqos,
-  output [1-1:0] myaxi_aruser,
+  output [2-1:0] myaxi_aruser,
   output reg myaxi_arvalid,
   input myaxi_arready,
   input [32-1:0] myaxi_rdata,

tests/extension/types_/axi_/memory_model_read/test_types_memory_model_read.py

@@ -16,7 +16,7 @@
   wire [4-1:0] myaxi_awcache;
   wire [3-1:0] myaxi_awprot;
   wire [4-1:0] myaxi_awqos;
-  wire [1-1:0] myaxi_awuser;
+  wire [2-1:0] myaxi_awuser;
   wire myaxi_awvalid;
   reg myaxi_awready;
   wire [32-1:0] myaxi_wdata;
@@ -35,7 +35,7 @@
   wire [4-1:0] myaxi_arcache;
   wire [3-1:0] myaxi_arprot;
   wire [4-1:0] myaxi_arqos;
-  wire [1-1:0] myaxi_aruser;
+  wire [2-1:0] myaxi_aruser;
   wire myaxi_arvalid;
   reg myaxi_arready;
   reg [32-1:0] myaxi_rdata;
@@ -51,7 +51,7 @@
   wire [4-1:0] memory_awcache;
   wire [3-1:0] memory_awprot;
   wire [4-1:0] memory_awqos;
-  wire [1-1:0] memory_awuser;
+  wire [2-1:0] memory_awuser;
   wire memory_awvalid;
   reg memory_awready;
   wire [32-1:0] memory_wdata;
@@ -70,7 +70,7 @@
   wire [4-1:0] memory_arcache;
   wire [3-1:0] memory_arprot;
   wire [4-1:0] memory_arqos;
-  wire [1-1:0] memory_aruser;
+  wire [2-1:0] memory_aruser;
   wire memory_arvalid;
   reg memory_arready;
   reg [32-1:0] memory_rdata;
@@ -532,7 +532,7 @@
   output [4-1:0] myaxi_awcache,
   output [3-1:0] myaxi_awprot,
   output [4-1:0] myaxi_awqos,
-  output [1-1:0] myaxi_awuser,
+  output [2-1:0] myaxi_awuser,
   output reg myaxi_awvalid,
   input myaxi_awready,
   output reg [32-1:0] myaxi_wdata,
@@ -551,7 +551,7 @@
   output [4-1:0] myaxi_arcache,
   output [3-1:0] myaxi_arprot,
   output [4-1:0] myaxi_arqos,
-  output [1-1:0] myaxi_aruser,
+  output [2-1:0] myaxi_aruser,
   output reg myaxi_arvalid,
   input myaxi_arready,
   input [32-1:0] myaxi_rdata,

tests/extension/types_/axi_/memory_model_write/test_types_memory_model_write.py

@@ -16,7 +16,7 @@
   wire [4-1:0] myaxi_awcache;
   wire [3-1:0] myaxi_awprot;
   wire [4-1:0] myaxi_awqos;
-  wire [1-1:0] myaxi_awuser;
+  wire [2-1:0] myaxi_awuser;
   wire myaxi_awvalid;
   reg myaxi_awready;
   wire [32-1:0] myaxi_wdata;
@@ -35,7 +35,7 @@
   wire [4-1:0] myaxi_arcache;
   wire [3-1:0] myaxi_arprot;
   wire [4-1:0] myaxi_arqos;
-  wire [1-1:0] myaxi_aruser;
+  wire [2-1:0] myaxi_aruser;
   wire myaxi_arvalid;
   reg myaxi_arready;
   reg [32-1:0] myaxi_rdata;
@@ -51,7 +51,7 @@
   wire [4-1:0] memory_awcache;
   wire [3-1:0] memory_awprot;
   wire [4-1:0] memory_awqos;
-  wire [1-1:0] memory_awuser;
+  wire [2-1:0] memory_awuser;
   wire memory_awvalid;
   reg memory_awready;
   wire [32-1:0] memory_wdata;
@@ -70,7 +70,7 @@
   wire [4-1:0] memory_arcache;
   wire [3-1:0] memory_arprot;
   wire [4-1:0] memory_arqos;
-  wire [1-1:0] memory_aruser;
+  wire [2-1:0] memory_aruser;
   wire memory_arvalid;
   reg memory_arready;
   reg [32-1:0] memory_rdata;
@@ -532,7 +532,7 @@
   output [4-1:0] myaxi_awcache,
   output [3-1:0] myaxi_awprot,
   output [4-1:0] myaxi_awqos,
-  output [1-1:0] myaxi_awuser,
+  output [2-1:0] myaxi_awuser,
   output reg myaxi_awvalid,
   input myaxi_awready,
   output reg [32-1:0] myaxi_wdata,
@@ -551,7 +551,7 @@
   output [4-1:0] myaxi_arcache,
   output [3-1:0] myaxi_arprot,
   output [4-1:0] myaxi_arqos,
-  output [1-1:0] myaxi_aruser,
+  output [2-1:0] myaxi_aruser,
   output reg myaxi_arvalid,
   input myaxi_arready,
   input [32-1:0] myaxi_rdata,

tests/extension/types_/axi_/ram_to_axi/test_types_axi_ram_to_axi.py

@@ -16,7 +16,7 @@
   wire [4-1:0] myaxi_awcache;
   wire [3-1:0] myaxi_awprot;
   wire [4-1:0] myaxi_awqos;
-  wire [1-1:0] myaxi_awuser;
+  wire [2-1:0] myaxi_awuser;
   wire myaxi_awvalid;
   reg myaxi_awready;
   wire [32-1:0] myaxi_wdata;
@@ -35,7 +35,7 @@
   wire [4-1:0] myaxi_arcache;
   wire [3-1:0] myaxi_arprot;
   wire [4-1:0] myaxi_arqos;
-  wire [1-1:0] myaxi_aruser;
+  wire [2-1:0] myaxi_aruser;
   wire myaxi_arvalid;
   reg myaxi_arready;
   reg [32-1:0] myaxi_rdata;
@@ -307,7 +307,7 @@
   output [4-1:0] myaxi_awcache,
   output [3-1:0] myaxi_awprot,
   output [4-1:0] myaxi_awqos,
-  output [1-1:0] myaxi_awuser,
+  output [2-1:0] myaxi_awuser,
   output reg myaxi_awvalid,
   input myaxi_awready,
   output reg [32-1:0] myaxi_wdata,
@@ -326,7 +326,7 @@
   output [4-1:0] myaxi_arcache,
   output [3-1:0] myaxi_arprot,
   output [4-1:0] myaxi_arqos,
-  output [1-1:0] myaxi_aruser,
+  output [2-1:0] myaxi_aruser,
   output reg myaxi_arvalid,
   input myaxi_arready,
   input [32-1:0] myaxi_rdata,