region accumulators are implemented.

Author: shtaxxx

tests/extension/dataflow_/iadd_enable/test_dataflow_iadd_enable.py

@@ -419,6 +419,9 @@
         _tmp_valid_0 <= xvalid && enablevalid && resetvalid;
       end 
       if((_tmp_ready_0 || !_tmp_valid_0) && (xready && enableready && resetready) && (xvalid && enablevalid && resetvalid) && resetdata) begin
+        _tmp_data_0 <= 1'd0;
+      end 
+      if((_tmp_ready_0 || !_tmp_valid_0) && (xready && enableready && resetready) && (xvalid && enablevalid && resetvalid) && enabledata && resetdata) begin
         _tmp_data_0 <= 1'd0 + xdata;
       end 
     end

tests/extension/dataflow_/ireg/test_dataflow_ireg.py

@@ -419,6 +419,9 @@
       if((_tmp_ready_0 || !_tmp_valid_0) && (xready && enableready && resetready) && (xvalid && enablevalid && resetvalid) && resetdata) begin
         _tmp_data_0 <= 1'd0;
       end 
+      if((_tmp_ready_0 || !_tmp_valid_0) && (xready && enableready && resetready) && (xvalid && enablevalid && resetvalid) && enabledata && resetdata) begin
+        _tmp_data_0 <= 1'd0;
+      end 
     end
   end
 

tests/extension/dataflow_/accadd/Makefile renamed to tests/extension/dataflow_/regionadd/Makefile

@@ -16,8 +16,8 @@ def mkMain():
     #enable = dataflow.Variable('enabledata', valid='enablevalid', ready='enableready', width=1)
 
     # dataflow definition
-    #z, v = dataflow.AccAdd(x, 4, initval=0, enable=enable, reset=reset)
-    z, v = dataflow.AccAdd(x, 4, initval=0)
+    #z, v = dataflow.RegionAdd(x, 4, initval=0, enable=enable, reset=reset)
+    z, v = dataflow.RegionAdd(x, 4, initval=0)
 
     # set output attribute
     z.output('zdata', valid='zvalid', ready='zready')

tests/extension/dataflow_/accadd/dataflow_accadd.py renamed to tests/extension/dataflow_/regionadd/dataflow_regionadd.py

@@ -1,7 +1,7 @@
 from __future__ import absolute_import
 from __future__ import print_function
 import veriloggen
-import dataflow_accadd
+import dataflow_regionadd
 
 expected_verilog = """
 module test;
@@ -466,7 +466,7 @@
 
 def test():
     veriloggen.reset()
-    test_module = dataflow_accadd.mkTest()
+    test_module = dataflow_regionadd.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser

tests/extension/dataflow_/accadd/test_dataflow_accadd.py renamed to tests/extension/dataflow_/regionadd/test_dataflow_regionadd.py

@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd 

tests/extension/dataflow_/regionadd_enable/Makefile

@@ -0,0 +1,219 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+import veriloggen.dataflow as dataflow
+
+def mkMain():
+    # input variiable
+    x = dataflow.Variable('xdata', valid='xvalid', ready='xready')
+    reset = dataflow.Variable('resetdata', valid='resetvalid', ready='resetready', width=1)
+    enable = dataflow.Variable('enabledata', valid='enablevalid', ready='enableready', width=1)
+
+    # dataflow definition
+    z, v = dataflow.RegionAdd(x, 4, initval=0, enable=enable, reset=reset)
+
+    # set output attribute
+    z.output('zdata', valid='zvalid', ready='zready')
+    v.output('vdata', valid='vvalid', ready='vready')
+
+    df = dataflow.Dataflow(z, v)
+    m = df.to_module('main')
+    #df.draw_graph()
+    
+    return m
+
+def mkTest(numports=8):
+    m = Module('test')
+
+    # target instance
+    main = mkMain()
+
+    params = m.copy_params(main)
+    ports = m.copy_sim_ports(main)
+
+    clk = ports['CLK']
+    rst = ports['RST']
+
+    xdata = ports['xdata']
+    xvalid = ports['xvalid']
+    xready = ports['xready']
+    
+    resetdata = ports['resetdata']
+    resetvalid = ports['resetvalid']
+    resetready = ports['resetready']
+    
+    enabledata = ports['enabledata']
+    enablevalid = ports['enablevalid']
+    enableready = ports['enableready']
+    
+    zdata = ports['zdata']
+    zvalid = ports['zvalid']
+    zready = ports['zready']
+    
+    vdata = ports['vdata']
+    vvalid = ports['vvalid']
+    vready = ports['vready']
+    
+    uut = m.Instance(main, 'uut',
+                     params=m.connect_params(main),
+                     ports=m.connect_ports(main))
+
+    reset_done = m.Reg('reset_done', initval=0)
+    reset_stmt = []
+    reset_stmt.append( reset_done(0) )
+    reset_stmt.append( xdata(0) )
+    reset_stmt.append( xvalid(0) )
+    reset_stmt.append( enabledata(0) )
+    reset_stmt.append( enablevalid(0) )
+    reset_stmt.append( resetdata(0) )
+    reset_stmt.append( resetvalid(0) )
+    reset_stmt.append( zready(0) )
+
+    simulation.setup_waveform(m, uut)
+    simulation.setup_clock(m, clk, hperiod=5)
+    init = simulation.setup_reset(m, rst, reset_stmt, period=100)
+
+    nclk = simulation.next_clock
+    
+    init.add(
+        Delay(1000),
+        reset_done(1),
+        nclk(clk),
+        Delay(10000),
+        Systask('finish'),
+    )
+ 
+
+    def send(name, data, valid, ready, step=1, waitnum=10, send_size=20):
+        fsm = FSM(m, name + 'fsm', clk, rst)
+        count = m.TmpReg(32, initval=0)
+        
+        fsm.add(valid(0))
+        fsm.goto_next(cond=reset_done)
+        for _ in range(waitnum):
+            fsm.goto_next()
+            
+        fsm.add(valid(1))
+        fsm.goto_next()
+        
+        fsm.add(data(data + step), cond=ready)
+        fsm.add(count.inc(), cond=ready)
+        fsm.add(valid(0), cond=AndList(count==5, ready))
+        fsm.goto_next(cond=AndList(count==5, ready))
+        
+        for _ in range(waitnum):
+            fsm.goto_next()
+        fsm.add(valid(1))
+        
+        fsm.add(data(data + step), cond=ready)
+        fsm.add(count.inc(), cond=ready)
+        fsm.add(valid(0), cond=AndList(count==send_size, ready))
+        fsm.goto_next(cond=AndList(count==send_size, ready))
+        
+        fsm.make_always()
+    
+
+    def receive(name, data, valid, ready, waitnum=10):
+        fsm = FSM(m, name + 'fsm', clk, rst)
+        
+        fsm.add(ready(0))
+        fsm.goto_next(cond=reset_done)
+        fsm.goto_next()
+        
+        yinit = fsm.current
+        fsm.add(ready(1), cond=valid)
+        fsm.goto_next(cond=valid)
+        for i in range(waitnum):
+            fsm.add(ready(0))
+            fsm.goto_next()
+            
+        fsm.goto(yinit)
+        
+        fsm.make_always()
+
+        
+    send('x', xdata, xvalid, xready, waitnum=10, send_size=100)
+    receive('z', zdata, zvalid, zready, waitnum=5)
+    receive('v', vdata, vvalid, vready, waitnum=5)
+
+    
+    # enable port
+    enable_fsm = FSM(m, 'enable', clk, rst)
+    enable_count = m.Reg('enable_count', 32, initval=0)
+
+    enable_fsm.goto_next(cond=reset_done)
+    
+    enable_fsm_init = enable_fsm.current
+
+    enable_fsm.add( enablevalid(1) ) # always High
+    
+    enable_fsm.add( enable_count.inc(), cond=AndList(enablevalid, enableready) )
+    enable_fsm.add( enabledata(1), cond=AndList(enablevalid, enableready, enable_count==2) )
+    enable_fsm.goto_next( cond=AndList(enablevalid, enableready, enable_count==2) )
+
+    enable_fsm.add( enabledata(0), cond=AndList(enablevalid, enableready) )
+    enable_fsm.add( enable_count(0) )
+    enable_fsm.goto(enable_fsm_init, cond=AndList(enablevalid, enableready) )
+
+    enable_fsm.make_always()
+
+    
+    # reset port
+    reset_fsm = FSM(m, 'reset', clk, rst)
+    reset_count = m.Reg('reset_count', 32, initval=0)
+
+    reset_fsm.goto_next(cond=reset_done)
+    
+    reset_fsm_init = reset_fsm.current
+
+    reset_fsm.add( resetvalid(1) ) # always High
+    
+    reset_fsm.add( reset_count.inc(), cond=AndList(resetvalid, resetready) )
+    #reset_fsm.add( resetdata(1), cond=AndList(resetvalid, resetready, reset_count==2) )
+    reset_fsm.add( resetdata(0), cond=AndList(resetvalid, resetready, reset_count==2) )
+    reset_fsm.goto_next( cond=AndList(resetvalid, resetready, reset_count==2) )
+
+    reset_fsm.add( resetdata(0), cond=AndList(resetvalid, resetready) )
+    reset_fsm.add( reset_count(0) )
+    reset_fsm.goto(reset_fsm_init, cond=AndList(resetvalid, resetready) )
+
+    reset_fsm.make_always()
+
+    
+    m.Always(Posedge(clk))(
+        If(reset_done)(
+            If(AndList(xvalid, xready))(
+                Systask('display', 'xdata=%d', xdata)
+            ),
+            If(AndList(zvalid, zready))(
+                Systask('display', 'zdata=%d', zdata)
+            ),
+            If(AndList(vvalid, vready))(
+                Systask('display', 'vdata=%d', vdata)
+            )
+        )
+    )
+    
+    return m
+
+    
+if __name__ == '__main__':
+    test = mkTest()
+    verilog = test.to_verilog('tmp.v')
+    print(verilog)
+
+    # run simulator (Icarus Verilog)
+    sim = simulation.Simulator(test)
+    rslt = sim.run() # display=False
+    #rslt = sim.run(display=True)
+    print(rslt)
+
+    # launch waveform viewer (GTKwave)
+    #sim.view_waveform() # background=False
+    #sim.view_waveform(background=True)