_implement_output_sig() in dataflow.dtypes checks whether output_sig_data and related signals are already assigned or not.

Author: shtaxxx

veriloggen/dataflow/dtypes.py

@@ -254,9 +254,10 @@ def _implement_output(self, m, seq, aswire=False):
         valid = self.output_sig_valid
         ready = self.output_sig_ready
 
-        m.Assign(data(self.sig_data))
+        if len(data.subst) == 0:
+            m.Assign(data(self.sig_data))
 
-        if self.output_valid is not None:
+        if self.output_valid is not None and len(valid.subst) == 0:
             m.Assign(valid(self.sig_valid))
 
         if self.output_ready is not None:
@@ -1525,6 +1526,7 @@ def OrList(*args):
         left = Lor(left, right)
     return left
 
+
 Ands = AndList
 Ors = OrList