renamed: lib/parallel.Parallel -> lib/seq.Seq

Author: shtaxxx

tests/lib_parallel_/Makefile renamed to tests/lib_seq_/Makefile

@@ -26,7 +26,7 @@ def mkLed(numports=8):
     odata = m.OutputReg('odata', 32, initval=0)
     ovalid = m.OutputReg('ovalid', initval=0)
 
-    par = lib.Parallel(m, 'par')
+    seq = lib.Seq(m, 'seq')
     pdata = idata
     pvalid = ivalid
     ndata = []
@@ -39,17 +39,17 @@ def mkLed(numports=8):
             ndata.append(td)
             nvalid.append(tv)
             cond = AndList(pvalid[i*2], pvalid[i*2+1])
-            par.add( td(pdata[i*2] + pdata[i*2+1]), cond=cond )
-            par.add( tv(cond) )
+            seq.add( td(pdata[i*2] + pdata[i*2+1]), cond=cond )
+            seq.add( tv(cond) )
         pdata = ndata
         pvalid = nvalid
         ndata = []
         nvalid = []
 
-    par.add( odata(pdata[-1]) )
-    par.add( ovalid(pvalid[-1]) )
+    seq.add( odata(pdata[-1]) )
+    seq.add( ovalid(pvalid[-1]) )
 
-    par.make_always(clk, rst)
+    seq.make_always(clk, rst)
 
     return m
 

tests/lib_parallel_/adder/Makefile renamed to tests/lib_seq_/adder/Makefile

@@ -1,4 +1,4 @@
-import lib_parallel_addr
+import lib_seq_addr
 
 expected_verilog = """
 module test;
@@ -285,7 +285,7 @@
 """
 
 def test():
-    test_module = lib_parallel_addr.mkTest()
+    test_module = lib_seq_addr.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser

tests/lib_parallel_/adder/lib_parallel_addr.py renamed to tests/lib_seq_/adder/lib_seq_addr.py

@@ -13,12 +13,12 @@ def mkLed():
     x = m.Input('x', 32)
     y = m.OutputReg('y', initval=0)
 
-    par = lib.Parallel(m, 'par')
-    par.add( y(0), cond=(x<10) )
-    par.add( y(1), cond=(x>=10) )
-    par.add( y(0), cond=(x>100) )
+    seq = lib.Seq(m, 'seq')
+    seq.add( y(0), cond=(x<10) )
+    seq.add( y(1), cond=(x>=10) )
+    seq.add( y(0), cond=(x>100) )
 
-    par.make_always(clk, rst)
+    seq.make_always(clk, rst)
 
     return m
 

tests/lib_parallel_/adder/test_lib_parallel_addr.py renamed to tests/lib_seq_/adder/test_lib_seq_addr.py

@@ -1,4 +1,4 @@
-import lib_parallel_cmp
+import lib_seq_cmp
 
 expected_verilog = """
 module test;
@@ -79,7 +79,7 @@
 """
 
 def test():
-    test_module = lib_parallel_cmp.mkTest()
+    test_module = lib_seq_cmp.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser

tests/lib_parallel_/cmp/Makefile renamed to tests/lib_seq_/cmp/Makefile

@@ -13,16 +13,16 @@ def mkLed(numports=8, delay_amount=2):
     rst = m.Input('RST')
     led = [ m.OutputReg('led'+str(i), initval=0) for i in range(numports) ]
 
-    par = lib.Parallel(m, 'par')
+    seq = lib.Seq(m, 'seq')
 
     count = m.Reg('count', (numports-1).bit_length(), initval=0)
-    par.add( count.inc() )
+    seq.add( count.inc() )
 
     for i in range(numports):
-        par.add( led[i](1), cond=(count==i) )
-        par.add( led[i](0), cond=(count==i), delay=delay_amount )
+        seq.add( led[i](1), cond=(count==i) )
+        seq.add( led[i](0), cond=(count==i), delay=delay_amount )
 
-    par.make_always(clk, rst)
+    seq.make_always(clk, rst)
 
     return m
 

tests/lib_parallel_/cmp/lib_parallel_cmp.py renamed to tests/lib_seq_/cmp/lib_seq_cmp.py

@@ -1,4 +1,4 @@
-import lib_parallel_delayed
+import lib_seq_delayed
 
 expected_verilog = """
 module test;
@@ -67,124 +67,124 @@
   );
 
   reg [3-1:0] count;
-  reg _par_cond_0_1;
-  reg _par_cond_0_2;
-  reg _par_cond_1_1;
-  reg _par_cond_1_2;
-  reg _par_cond_2_1;
-  reg _par_cond_2_2;
-  reg _par_cond_3_1;
-  reg _par_cond_3_2;
-  reg _par_cond_4_1;
-  reg _par_cond_4_2;
-  reg _par_cond_5_1;
-  reg _par_cond_5_2;
-  reg _par_cond_6_1;
-  reg _par_cond_6_2;
-  reg _par_cond_7_1;
-  reg _par_cond_7_2;
+  reg _seq_cond_0_1;
+  reg _seq_cond_0_2;
+  reg _seq_cond_1_1;
+  reg _seq_cond_1_2;
+  reg _seq_cond_2_1;
+  reg _seq_cond_2_2;
+  reg _seq_cond_3_1;
+  reg _seq_cond_3_2;
+  reg _seq_cond_4_1;
+  reg _seq_cond_4_2;
+  reg _seq_cond_5_1;
+  reg _seq_cond_5_2;
+  reg _seq_cond_6_1;
+  reg _seq_cond_6_2;
+  reg _seq_cond_7_1;
+  reg _seq_cond_7_2;
 
   always @(posedge CLK) begin
     if(RST) begin
       count <= 0;
       led0 <= 0;
-      _par_cond_0_1 <= 0;
-      _par_cond_0_2 <= 0;
+      _seq_cond_0_1 <= 0;
+      _seq_cond_0_2 <= 0;
       led1 <= 0;
-      _par_cond_1_1 <= 0;
-      _par_cond_1_2 <= 0;
+      _seq_cond_1_1 <= 0;
+      _seq_cond_1_2 <= 0;
       led2 <= 0;
-      _par_cond_2_1 <= 0;
-      _par_cond_2_2 <= 0;
+      _seq_cond_2_1 <= 0;
+      _seq_cond_2_2 <= 0;
       led3 <= 0;
-      _par_cond_3_1 <= 0;
-      _par_cond_3_2 <= 0;
+      _seq_cond_3_1 <= 0;
+      _seq_cond_3_2 <= 0;
       led4 <= 0;
-      _par_cond_4_1 <= 0;
-      _par_cond_4_2 <= 0;
+      _seq_cond_4_1 <= 0;
+      _seq_cond_4_2 <= 0;
       led5 <= 0;
-      _par_cond_5_1 <= 0;
-      _par_cond_5_2 <= 0;
+      _seq_cond_5_1 <= 0;
+      _seq_cond_5_2 <= 0;
       led6 <= 0;
-      _par_cond_6_1 <= 0;
-      _par_cond_6_2 <= 0;
+      _seq_cond_6_1 <= 0;
+      _seq_cond_6_2 <= 0;
       led7 <= 0;
-      _par_cond_7_1 <= 0;
-      _par_cond_7_2 <= 0;
+      _seq_cond_7_1 <= 0;
+      _seq_cond_7_2 <= 0;
     end else begin
-      if(_par_cond_0_2) begin
+      if(_seq_cond_0_2) begin
         led0 <= 0;
       end 
-      if(_par_cond_1_2) begin
+      if(_seq_cond_1_2) begin
         led1 <= 0;
       end 
-      if(_par_cond_2_2) begin
+      if(_seq_cond_2_2) begin
         led2 <= 0;
       end 
-      if(_par_cond_3_2) begin
+      if(_seq_cond_3_2) begin
         led3 <= 0;
       end 
-      if(_par_cond_4_2) begin
+      if(_seq_cond_4_2) begin
         led4 <= 0;
       end 
-      if(_par_cond_5_2) begin
+      if(_seq_cond_5_2) begin
         led5 <= 0;
       end 
-      if(_par_cond_6_2) begin
+      if(_seq_cond_6_2) begin
         led6 <= 0;
       end 
-      if(_par_cond_7_2) begin
+      if(_seq_cond_7_2) begin
         led7 <= 0;
       end 
-      _par_cond_0_2 <= _par_cond_0_1;
-      _par_cond_1_2 <= _par_cond_1_1;
-      _par_cond_2_2 <= _par_cond_2_1;
-      _par_cond_3_2 <= _par_cond_3_1;
-      _par_cond_4_2 <= _par_cond_4_1;
-      _par_cond_5_2 <= _par_cond_5_1;
-      _par_cond_6_2 <= _par_cond_6_1;
-      _par_cond_7_2 <= _par_cond_7_1;
+      _seq_cond_0_2 <= _seq_cond_0_1;
+      _seq_cond_1_2 <= _seq_cond_1_1;
+      _seq_cond_2_2 <= _seq_cond_2_1;
+      _seq_cond_3_2 <= _seq_cond_3_1;
+      _seq_cond_4_2 <= _seq_cond_4_1;
+      _seq_cond_5_2 <= _seq_cond_5_1;
+      _seq_cond_6_2 <= _seq_cond_6_1;
+      _seq_cond_7_2 <= _seq_cond_7_1;
       count <= count + 1;
       if(count == 0) begin
         led0 <= 1;
       end 
-      _par_cond_0_1 <= (count == 0);
+      _seq_cond_0_1 <= (count == 0);
       if(count == 1) begin
         led1 <= 1;
       end 
-      _par_cond_1_1 <= (count == 1);
+      _seq_cond_1_1 <= (count == 1);
       if(count == 2) begin
         led2 <= 1;
       end 
-      _par_cond_2_1 <= (count == 2);
+      _seq_cond_2_1 <= (count == 2);
       if(count == 3) begin
         led3 <= 1;
       end 
-      _par_cond_3_1 <= (count == 3);
+      _seq_cond_3_1 <= (count == 3);
       if(count == 4) begin
         led4 <= 1;
       end 
-      _par_cond_4_1 <= (count == 4);
+      _seq_cond_4_1 <= (count == 4);
       if(count == 5) begin
         led5 <= 1;
       end 
-      _par_cond_5_1 <= (count == 5);
+      _seq_cond_5_1 <= (count == 5);
       if(count == 6) begin
         led6 <= 1;
       end 
-      _par_cond_6_1 <= (count == 6);
+      _seq_cond_6_1 <= (count == 6);
       if(count == 7) begin
         led7 <= 1;
       end 
-      _par_cond_7_1 <= (count == 7);
+      _seq_cond_7_1 <= (count == 7);
     end
   end
 
 endmodule
 """
 
 def test():
-    test_module = lib_parallel_delayed.mkTest()
+    test_module = lib_seq_delayed.mkTest()
     code = test_module.to_verilog()
 
     from pyverilog.vparser.parser import VerilogParser