Merge branch 'feature_optimize_axim' into develop

Author: shtaxxx

examples/simulation_verilator/test_simulation_verilator.py

@@ -1116,7 +1116,7 @@
   localparam write_burst_fsm_0_init = 0;
   reg [10-1:0] write_burst_addr_30;
   reg [10-1:0] write_burst_stride_31;
-  reg [11-1:0] write_burst_length_32;
+  reg [33-1:0] write_burst_length_32;
   reg write_burst_done_33;
   assign ram_a_0_wdata = ((write_burst_fsm_0 == 1) && myaxi_rvalid)? myaxi_rdata : 'hx;
   assign ram_a_0_wenable = ((write_burst_fsm_0 == 1) && myaxi_rvalid)? 1'd1 : 0;
@@ -1130,7 +1130,7 @@
   localparam write_burst_fsm_1_init = 0;
   reg [10-1:0] write_burst_addr_36;
   reg [10-1:0] write_burst_stride_37;
-  reg [11-1:0] write_burst_length_38;
+  reg [33-1:0] write_burst_length_38;
   reg write_burst_done_39;
   assign ram_b_0_wdata = ((write_burst_fsm_1 == 1) && myaxi_rvalid)? myaxi_rdata : 'hx;
   assign ram_b_0_wenable = ((write_burst_fsm_1 == 1) && myaxi_rvalid)? 1'd1 : 0;
@@ -1227,7 +1227,7 @@
   localparam read_burst_fsm_2_init = 0;
   reg [10-1:0] read_burst_addr_74;
   reg [10-1:0] read_burst_stride_75;
-  reg [11-1:0] read_burst_length_76;
+  reg [33-1:0] read_burst_length_76;
   reg read_burst_rvalid_77;
   reg read_burst_rlast_78;
   localparam _tmp_79 = 1;
@@ -1259,7 +1259,7 @@
   localparam write_burst_fsm_3_init = 0;
   reg [10-1:0] write_burst_addr_84;
   reg [10-1:0] write_burst_stride_85;
-  reg [11-1:0] write_burst_length_86;
+  reg [33-1:0] write_burst_length_86;
   reg write_burst_done_87;
   assign ram_c_0_wdata = ((write_burst_fsm_3 == 1) && myaxi_rvalid)? myaxi_rdata : 
                          (th_matmul == 22)? _th_matmul_sum_14 : 'hx;

examples/stream_axi_stream_fifo_ipxact_ultra96v2_pynq/test_stream_axi_stream_fifo_ipxact.py

@@ -640,7 +640,7 @@
   localparam write_burst_fsm_0_init = 0;
   reg [10-1:0] write_burst_addr_43;
   reg [10-1:0] write_burst_stride_44;
-  reg [11-1:0] write_burst_length_45;
+  reg [33-1:0] write_burst_length_45;
   reg write_burst_done_46;
   assign ram_b_0_wdata = ((write_burst_fsm_0 == 1) && maxi_rvalid)? maxi_rdata : 'hx;
   assign ram_b_0_wenable = ((write_burst_fsm_0 == 1) && maxi_rvalid)? 1'd1 : 0;

examples/stream_axi_stream_fifo_ultra96v2_pynq/test_stream_axi_stream_fifo.py

@@ -640,7 +640,7 @@
   localparam write_burst_fsm_0_init = 0;
   reg [10-1:0] write_burst_addr_43;
   reg [10-1:0] write_burst_stride_44;
-  reg [11-1:0] write_burst_length_45;
+  reg [33-1:0] write_burst_length_45;
   reg write_burst_done_46;
   assign ram_b_0_wdata = ((write_burst_fsm_0 == 1) && maxi_rvalid)? maxi_rdata : 'hx;
   assign ram_b_0_wenable = ((write_burst_fsm_0 == 1) && maxi_rvalid)? 1'd1 : 0;

examples/thread_embedded_verilog_ipxact/test_thread_embedded_verilog_ipxact.py

@@ -1659,7 +1659,7 @@
   localparam write_burst_fsm_0_init = 0;
   reg [10-1:0] write_burst_addr_39;
   reg [10-1:0] write_burst_stride_40;
-  reg [11-1:0] write_burst_length_41;
+  reg [33-1:0] write_burst_length_41;
   reg write_burst_done_42;
   assign ram_a_0_wdata = ((write_burst_fsm_0 == 1) && maxi_rvalid)? maxi_rdata : 'hx;
   assign ram_a_0_wenable = ((write_burst_fsm_0 == 1) && maxi_rvalid)? 1'd1 : 0;
@@ -1735,7 +1735,7 @@
   localparam read_burst_fsm_1_init = 0;
   reg [10-1:0] read_burst_addr_71;
   reg [10-1:0] read_burst_stride_72;
-  reg [11-1:0] read_burst_length_73;
+  reg [33-1:0] read_burst_length_73;
   reg read_burst_rvalid_74;
   reg read_burst_rlast_75;
   assign ram_a_0_addr = ((read_burst_fsm_1 == 1) && (!read_burst_rvalid_74 || (maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0)))? read_burst_addr_71 : 

examples/thread_memcpy_ipxact_ultra96v2_pynq/test_thread_memcpy_ipxact.py

@@ -1642,7 +1642,7 @@
   localparam write_burst_fsm_0_init = 0;
   reg [10-1:0] write_burst_addr_39;
   reg [10-1:0] write_burst_stride_40;
-  reg [11-1:0] write_burst_length_41;
+  reg [33-1:0] write_burst_length_41;
   reg write_burst_done_42;
   assign ram_a_0_wdata = ((write_burst_fsm_0 == 1) && maxi_rvalid)? maxi_rdata : 'hx;
   assign ram_a_0_wenable = ((write_burst_fsm_0 == 1) && maxi_rvalid)? 1'd1 : 0;
@@ -1718,7 +1718,7 @@
   localparam read_burst_fsm_1_init = 0;
   reg [10-1:0] read_burst_addr_71;
   reg [10-1:0] read_burst_stride_72;
-  reg [11-1:0] read_burst_length_73;
+  reg [33-1:0] read_burst_length_73;
   reg read_burst_rvalid_74;
   reg read_burst_rlast_75;
   assign ram_a_0_addr = ((read_burst_fsm_1 == 1) && (!read_burst_rvalid_74 || (maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0)))? read_burst_addr_71 : 

examples/thread_verilog_submodule_ipxact/test_thread_verilog_submodule_ipxact.py

@@ -1688,7 +1688,7 @@
   localparam write_burst_fsm_0_init = 0;
   reg [10-1:0] write_burst_addr_39;
   reg [10-1:0] write_burst_stride_40;
-  reg [11-1:0] write_burst_length_41;
+  reg [33-1:0] write_burst_length_41;
   reg write_burst_done_42;
   assign ram_a_0_wdata = ((write_burst_fsm_0 == 1) && maxi_rvalid)? maxi_rdata : 'hx;
   assign ram_a_0_wenable = ((write_burst_fsm_0 == 1) && maxi_rvalid)? 1'd1 : 0;
@@ -1765,7 +1765,7 @@
   localparam read_burst_fsm_1_init = 0;
   reg [10-1:0] read_burst_addr_71;
   reg [10-1:0] read_burst_stride_72;
-  reg [11-1:0] read_burst_length_73;
+  reg [33-1:0] read_burst_length_73;
   reg read_burst_rvalid_74;
   reg read_burst_rlast_75;
   assign ram_a_0_addr = ((read_burst_fsm_1 == 1) && (!read_burst_rvalid_74 || (maxi_wready || !maxi_wvalid) && (_maxi_write_size_buf > 0)))? read_burst_addr_71 : 

tests/extension/thread_/multibank_ram_dma/thread_multibank_ram_dma.py

@@ -18,7 +18,7 @@ def mkLed(memory_datawidth=128):
     rst = m.Input('RST')
 
     datawidth = 32
-    addrwidth = 10
+    addrwidth = 4
     numbanks = 4
     myaxi = vthread.AXIM(m, 'myaxi', clk, rst, memory_datawidth)
     myram0 = vthread.MultibankRAM(m, 'myram0', clk, rst, datawidth, addrwidth,

tests/extension/thread_/multibank_ram_dma_block/thread_multibank_ram_dma_block.py

@@ -18,7 +18,7 @@ def mkLed(memory_datawidth=32):
     rst = m.Input('RST')
 
     datawidth = 32
-    addrwidth = 10
+    addrwidth = 4
     numbanks = 4
     myaxi = vthread.AXIM(m, 'myaxi', clk, rst, memory_datawidth)
     myram0 = vthread.MultibankRAM(m, 'myram0', clk, rst, datawidth, addrwidth,

tests/extension/thread_/stream_axi_stream/test_thread_stream_axi_stream.py

@@ -416,7 +416,7 @@
   localparam write_burst_fsm_0_init = 0;
   reg [10-1:0] write_burst_addr_28;
   reg [10-1:0] write_burst_stride_29;
-  reg [11-1:0] write_burst_length_30;
+  reg [33-1:0] write_burst_length_30;
   reg write_burst_done_31;
   assign ram_a_1_addr = ((write_burst_fsm_0 == 1) && axi_a_tvalid)? write_burst_addr_28 : 'hx;
   assign ram_a_1_wdata = ((write_burst_fsm_0 == 1) && axi_a_tvalid)? axi_a_tdata : 'hx;
@@ -446,7 +446,7 @@
   localparam write_burst_fsm_1_init = 0;
   reg [10-1:0] write_burst_addr_39;
   reg [10-1:0] write_burst_stride_40;
-  reg [11-1:0] write_burst_length_41;
+  reg [33-1:0] write_burst_length_41;
   reg write_burst_done_42;
   assign ram_b_1_addr = ((write_burst_fsm_1 == 1) && axi_b_tvalid)? write_burst_addr_39 : 'hx;
   assign ram_b_1_wdata = ((write_burst_fsm_1 == 1) && axi_b_tvalid)? axi_b_tdata : 'hx;
@@ -552,7 +552,7 @@
   localparam read_burst_fsm_2_init = 0;
   reg [10-1:0] read_burst_addr_83;
   reg [10-1:0] read_burst_stride_84;
-  reg [11-1:0] read_burst_length_85;
+  reg [33-1:0] read_burst_length_85;
   reg read_burst_rvalid_86;
   reg read_burst_rlast_87;
   assign ram_c_1_addr = ((read_burst_fsm_2 == 1) && (!read_burst_rvalid_86 || (axi_c_tready || !axi_c_tvalid)))? read_burst_addr_83 : 'hx;

tests/extension/thread_/stream_axi_stream_async/test_thread_stream_axi_stream_async.py

@@ -416,7 +416,7 @@
   localparam write_burst_fsm_0_init = 0;
   reg [10-1:0] write_burst_addr_28;
   reg [10-1:0] write_burst_stride_29;
-  reg [11-1:0] write_burst_length_30;
+  reg [33-1:0] write_burst_length_30;
   reg write_burst_done_31;
   assign ram_a_1_addr = ((write_burst_fsm_0 == 1) && axi_a_tvalid)? write_burst_addr_28 : 'hx;
   assign ram_a_1_wdata = ((write_burst_fsm_0 == 1) && axi_a_tvalid)? axi_a_tdata : 'hx;
@@ -446,7 +446,7 @@
   localparam write_burst_fsm_1_init = 0;
   reg [10-1:0] write_burst_addr_39;
   reg [10-1:0] write_burst_stride_40;
-  reg [11-1:0] write_burst_length_41;
+  reg [33-1:0] write_burst_length_41;
   reg write_burst_done_42;
   assign ram_b_1_addr = ((write_burst_fsm_1 == 1) && axi_b_tvalid)? write_burst_addr_39 : 'hx;
   assign ram_b_1_wdata = ((write_burst_fsm_1 == 1) && axi_b_tvalid)? axi_b_tdata : 'hx;
@@ -552,7 +552,7 @@
   localparam read_burst_fsm_2_init = 0;
   reg [10-1:0] read_burst_addr_83;
   reg [10-1:0] read_burst_stride_84;
-  reg [11-1:0] read_burst_length_85;
+  reg [33-1:0] read_burst_length_85;
   reg read_burst_rvalid_86;
   reg read_burst_rlast_87;
   assign ram_c_1_addr = ((read_burst_fsm_2 == 1) && (!read_burst_rvalid_86 || (axi_c_tready || !axi_c_tvalid)))? read_burst_addr_83 : 'hx;