stream.CustomAcc

shtaxxx · shtaxxx · commit 0cd95f270bb2 · 2021-03-11T00:04:13.000+09:00
diff --git a/tests/extension/thread_/stream_custom_acc/Makefile b/tests/extension/thread_/stream_custom_acc/Makefile
@@ -0,0 +1,29 @@
+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd
diff --git a/tests/extension/thread_/stream_custom_acc/test_thread_stream_custom_acc.py b/tests/extension/thread_/stream_custom_acc/test_thread_stream_custom_acc.py
@@ -0,0 +1,18 @@
+from __future__ import absolute_import
+from __future__ import print_function
+
+import os
+import veriloggen
+import thread_stream_custom_acc
+
+
+def test(request):
+    veriloggen.reset()
+
+    simtype = request.config.getoption('--sim')
+
+    rslt = thread_stream_custom_acc.run(filename=None, simtype=simtype,
+                                        outputfile=os.path.splitext(os.path.basename(__file__))[0] + '.out')
+
+    verify_rslt = rslt.splitlines()[-1]
+    assert(verify_rslt == '# verify: PASSED')
diff --git a/tests/extension/thread_/stream_custom_acc/thread_stream_custom_acc.py b/tests/extension/thread_/stream_custom_acc/thread_stream_custom_acc.py
@@ -0,0 +1,170 @@
+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+import veriloggen.thread as vthread
+import veriloggen.types.axi as axi
+
+
+def mkLed():
+    m = Module('blinkled')
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+
+    datawidth = 32
+    addrwidth = 10
+    myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth)
+    ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth)
+    ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth)
+    ram_c = vthread.RAM(m, 'ram_c', clk, rst, datawidth, addrwidth)
+
+    strm = vthread.Stream(m, 'mystream', clk, rst)
+    size = strm.parameter('size')
+    a = strm.source('a')
+    b = strm.source('b')
+
+    def op_func(x, y, x_size, y_size):
+        x_cond = x == x_size - 1
+        next_x = Mux(x_cond, 0, x + 1)
+        y_cond = Ands(x_cond, y == y_size - 1)
+        next_y = Mux(y_cond, 0, y + 1)
+        return next_x, next_y
+
+    x, y = strm.CustomAcc(func=op_func,
+                          initvals=(0, 0), args=(size, size),
+                          width_list=(32, 32), signed_list=(True, True))
+
+    c = a + b + x + y
+    strm.sink(c, 'c')
+
+    def comp_stream(size, offset):
+        strm.set_parameter('size', size)
+        strm.set_source('a', ram_a, offset, size)
+        strm.set_source('b', ram_b, offset, size)
+        strm.set_sink('c', ram_c, offset, size)
+        strm.run()
+        strm.join()
+
+    def comp_sequential(size, offset):
+        sum = 0
+        x = 0
+        y = 0
+        x_size = size
+        y_size = size
+        for i in range(size):
+            a = ram_a.read(i + offset)
+            b = ram_b.read(i + offset)
+            sum = a + b + x + y
+            ram_c.write(i + offset, sum)
+            x_cond = x == x_size - 1
+            if x_cond:
+                x = 0
+            else:
+                x = x + 1
+            y_cond = x_cond and (y == y_size - 1)
+            if y_cond:
+                y = 0
+            else:
+                y = y + 1
+
+    def check(size, offset_stream, offset_seq):
+        all_ok = True
+        for i in range(size):
+            st = ram_c.read(i + offset_stream)
+            sq = ram_c.read(i + offset_seq)
+            if vthread.verilog.NotEql(st, sq):
+                all_ok = False
+        if all_ok:
+            print('# verify: PASSED')
+        else:
+            print('# verify: FAILED')
+
+    def comp(size):
+        # stream
+        offset = 0
+        myaxi.dma_read(ram_a, offset, 0, size)
+        myaxi.dma_read(ram_b, offset, 512, size)
+        comp_stream(size, offset)
+        myaxi.dma_write(ram_c, offset, 1024, size)
+
+        # sequential
+        offset = size
+        myaxi.dma_read(ram_a, offset, 0, size)
+        myaxi.dma_read(ram_b, offset, 512, size)
+        comp_sequential(size, offset)
+        myaxi.dma_write(ram_c, offset, 1024 * 2, size)
+
+        # verification
+        myaxi.dma_read(ram_c, 0, 1024, size)
+        myaxi.dma_read(ram_c, offset, 1024 * 2, size)
+        check(size, 0, offset)
+
+        vthread.finish()
+
+    th = vthread.Thread(m, 'th_comp', clk, rst, comp)
+    fsm = th.start(32)
+
+    return m
+
+
+def mkTest(memimg_name=None):
+    m = Module('test')
+
+    # target instance
+    led = mkLed()
+
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+
+    clk = ports['CLK']
+    rst = ports['RST']
+
+    memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name)
+    memory.connect(ports, 'myaxi')
+
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+
+    # simulation.setup_waveform(m, uut)
+    simulation.setup_clock(m, clk, hperiod=5)
+    init = simulation.setup_reset(m, rst, m.make_reset(), period=100)
+
+    init.add(
+        Delay(1000000),
+        Systask('finish'),
+    )
+
+    return m
+
+
+def run(filename='tmp.v', simtype='iverilog', outputfile=None):
+
+    if outputfile is None:
+        outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out'
+
+    memimg_name = 'memimg_' + outputfile
+
+    test = mkTest(memimg_name=memimg_name)
+
+    if filename is not None:
+        test.to_verilog(filename)
+
+    sim = simulation.Simulator(test, sim=simtype)
+    rslt = sim.run(outputfile=outputfile)
+    lines = rslt.splitlines()
+    if simtype == 'verilator' and lines[-1].startswith('-'):
+        rslt = '\n'.join(lines[:-1])
+    return rslt
+
+
+if __name__ == '__main__':
+    rslt = run(filename='tmp.v')
+    print(rslt)
diff --git a/veriloggen/stream/stypes.py b/veriloggen/stream/stypes.py
@@ -3729,6 +3729,146 @@ def CounterValid(size, step=1, interval=None, initval=0, offset=None,
     return data, valid
 
 
+class _CustomAcc(_SpecialOperator):
+    latency = 1
+
+    default_width = 32
+    default_point = 0
+    default_signed = True
+
+    def __init__(self, func, initvals, args=None, reset=None,
+                 width_list=None, point_list=None, signed_list=None):
+
+        _args = list(initvals)
+
+        if args is not None:
+            _args.extend(args)
+
+        if reset is not None:
+            _args.append(reset)
+
+        _SpecialOperator.__init__(self, *_args)
+
+        self.func = func
+        self.reset = self.args[-1] if reset is not None else None
+        self.num_vars = len(initvals)
+
+        if width_list is not None:
+            if len(width_list) != self.num_vars:
+                raise ValueError('width_list must have %d values, not %d.' %
+                                 (self.num_vars, len(width_list)))
+
+            total_width = 0
+            for width in width_list:
+                total_width += width
+
+        else:
+            total_width = self.default_width * self.num_vars
+            width_list = [self.default_width] * self.num_vars
+
+        self.width = total_width
+        self.width_list = width_list
+
+        if signed_list is not None:
+            if len(signed_list) != self.num_vars:
+                raise ValueError('signed_list must have %d values, not %d.' %
+                                 (self.num_vars, len(signed_list)))
+
+        else:
+            signed_list = [self.default_signed] * self.num_vars
+
+        self.signed = False
+        self.signed_list = signed_list
+
+        if point_list is not None:
+            if len(point_list) != self.num_vars:
+                raise ValueError('point_list must have %d values, not %d.' %
+                                 (self.num_vars, len(point_list)))
+        else:
+            point_list = [self.default_point] * self.num_vars
+
+        self.point = 0
+        self.point_list = point_list
+
+    def _implement(self, m, seq, svalid=None, senable=None):
+        if self.latency != 1:
+            raise ValueError("Latency must be '%d', not '%d'" %
+                             (self.latency, 1))
+
+        width = self.get_width()
+        signed = self.get_signed()
+
+        arg_data = [arg.sig_data for arg in self.args]
+
+        enable_cond = senable
+        if self.iteration_interval != 1:
+            enable_cond = _and_vars(enable_cond, svalid)
+
+        resetdata = arg_data[-1] if self.reset is not None else None
+
+        vars = [m.Reg(self.name('var_%d' % i), var_width, initval=0, signed=var_signed)
+                for i, (var_width, var_point, var_signed) in enumerate(
+            zip(self.width_list, self.point_list, self.signed_list))]
+
+        data = m.Wire(self.name('data'), width, signed=signed)
+        data.assign(vtypes.Cat(*vars))
+        self.sig_data = data
+
+        args = arg_data[self.num_vars:self.num_vars + self.num_vars]
+        func_args = vars + args
+        next_vars = self.func(*func_args)
+
+        if len(next_vars) != len(vars):
+            raise ValueError('CustomAcc function must return %d values.' % len(vars))
+
+        for var, next_var in zip(vars, next_vars):
+            seq(var(next_var), cond=enable_cond)
+
+        initvals = arg_data[:self.num_vars]
+
+        if resetdata is not None:
+            reset_cond = _and_vars(enable_cond, resetdata)
+            for var, initval in zip(vars, initvals):
+                seq(var(initval), cond=reset_cond)
+
+        # multicycle control
+        if self.iteration_interval != 1:
+            ii_count = m.Reg(self.name('ii_count'),
+                             int(ceil(log(self.iteration_interval, 2))) + 1, initval=0)
+            ii_stall_cond = m.Wire(self.name('ii_stall_cond'))
+            ii_stall_cond.assign(ii_count > 0)
+            util.add_disable_cond(self.strm.internal_oready,
+                                  ii_stall_cond, vtypes.Int(0))
+
+            seq.If(ii_count == 0, enable_cond)(
+                ii_count.inc()
+            )
+            seq.If(ii_count > 0)(
+                ii_count.inc()
+            )
+            seq.If(ii_count == self.iteration_interval - 1)(
+                ii_count(0)
+            )
+
+
+def CustomAcc(func, initvals, args=None, reset=None,
+              width_list=None, point_list=None, signed_list=None):
+
+    v = _CustomAcc(func, initvals, args, reset,
+                   width_list, point_list, signed_list)
+
+    return_values = []
+
+    s = 0
+    for width, point, signed in zip(reversed(v.width_list), reversed(v.point_list), reversed(v.signed_list)):
+        r = Slice(v, s + width - 1, s)
+        r = Cast(r, width=width, point=point, signed=signed)
+        s += width
+        return_values.append(r)
+
+    return tuple(reversed(return_values))
+
+
 class Int(_Constant):
 
     def __init__(self, value, signed=True):
diff --git a/veriloggen/thread/stream.py b/veriloggen/thread/stream.py
@@ -3761,7 +3761,8 @@ def __getattr__(self, attr):
             (f.__name__.startswith('Reduce') or
              f.__name__.startswith('Counter') or
              f.__name__.startswith('Pulse') or
-             f.__name__.startswith('Producer'))):
+             f.__name__.startswith('Producer') or
+             f.__name__.startswith('CustomAcc'))):
 
             if self.reduce_reset is None:
                 self._make_reduce_reset()
