Skip to content

Commit 08f856f

Browse files
shtaxxxshtaxxx
committed
TmpReg/TmpWire with prefix
1 parent 8b604c9 commit 08f856f

File tree

1 file changed

+52
-48
lines changed

1 file changed

+52
-48
lines changed

‎veriloggen/types/axi.py‎

Lines changed: 52 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -716,7 +716,8 @@ def write_request_counter(self, addr, length=1, cond=None, counter=None):
716716
ack = vtypes.Ors(self.waddr.awready, vtypes.Not(self.waddr.awvalid))
717717

718718
if counter is None:
719-
counter = self.m.TmpReg(self.burst_size_width + 1, initval=0)
719+
counter = self.m.TmpReg(self.burst_size_width + 1, initval=0,
720+
prefix='counter')
720721

721722
self.write_counters.append(counter)
722723

@@ -761,7 +762,7 @@ def write_data(self, data, counter=None, cond=None):
761762

762763
ack = vtypes.Ands(counter > 0,
763764
vtypes.Ors(self.wdata.wready, vtypes.Not(self.wdata.wvalid)))
764-
last = self.m.TmpReg(initval=0)
765+
last = self.m.TmpReg(initval=0, prefix='last')
765766

766767
self.seq.If(vtypes.Ands(ack, counter > 0))(
767768
self.wdata.wdata(data),
@@ -808,7 +809,7 @@ def write_dataflow(self, data, counter=None, cond=None, when=None):
808809

809810
ack = vtypes.Ands(counter > 0,
810811
vtypes.Ors(self.wdata.wready, vtypes.Not(self.wdata.wvalid)))
811-
last = self.m.TmpReg(initval=0)
812+
last = self.m.TmpReg(initval=0, prefix='last')
812813

813814
if cond is None:
814815
cond = ack
@@ -919,7 +920,7 @@ def read_request_counter(self, addr, length=1, cond=None, counter=None):
919920
ack = vtypes.Ors(self.raddr.arready, vtypes.Not(self.raddr.arvalid))
920921

921922
if counter is None:
922-
counter = self.m.TmpReg(self.burst_size_width + 1, initval=0)
923+
counter = self.m.TmpReg(self.burst_size_width + 1, initval=0, prefix='counter')
923924

924925
self.read_counters.append(counter)
925926

@@ -985,8 +986,8 @@ def read_dataflow(self, counter=None, cond=None, point=0, signed=True):
985986
if counter is None:
986987
counter = self.read_counters[-1]
987988

988-
data_ready = self.m.TmpWire()
989-
last_ready = self.m.TmpWire()
989+
data_ready = self.m.TmpWire(prefix='data_ready')
990+
last_ready = self.m.TmpWire(prefix='last_ready')
990991
data_ready.assign(1)
991992
last_ready.assign(1)
992993

@@ -1531,22 +1532,22 @@ def pull_request_counter(self, cond, counter=None):
15311532
raise TypeError("counter must be Reg or None.")
15321533

15331534
if counter is None:
1534-
counter = self.m.TmpReg(self.burst_size_width + 1, initval=0)
1535+
counter = self.m.TmpReg(self.burst_size_width + 1, initval=0, prefix='counter')
15351536

15361537
ready = make_condition(cond)
15371538

15381539
write_ack = vtypes.Ands(self.waddr.awready, self.waddr.awvalid,
15391540
vtypes.Not(self.wresp.bvalid))
15401541
read_ack = vtypes.Ands(self.raddr.arready, self.raddr.arvalid)
1541-
addr = self.m.TmpReg(self.addrwidth, initval=0)
1542-
writevalid = self.m.TmpReg(initval=0)
1543-
readvalid = self.m.TmpReg(initval=0)
1542+
addr = self.m.TmpReg(self.addrwidth, initval=0, prefix='addr')
1543+
writevalid = self.m.TmpReg(initval=0, prefix='writevalid')
1544+
readvalid = self.m.TmpReg(initval=0, prefix='readvalid')
15441545

1545-
prev_awvalid = self.m.TmpReg(initval=0)
1546+
prev_awvalid = self.m.TmpReg(initval=0, prefix='prev_awvalid')
15461547
self.seq(
15471548
prev_awvalid(self.waddr.awvalid)
15481549
)
1549-
prev_arvalid = self.m.TmpReg(initval=0)
1550+
prev_arvalid = self.m.TmpReg(initval=0, prefix='prev_arvalid')
15501551
self.seq(
15511552
prev_arvalid(self.raddr.arvalid)
15521553
)
@@ -1595,18 +1596,19 @@ def pull_write_request_counter(self, cond=None, counter=None):
15951596
raise TypeError("counter must be Reg or None.")
15961597

15971598
if counter is None:
1598-
counter = self.m.TmpReg(self.burst_size_width + 1, initval=0)
1599+
counter = self.m.TmpReg(self.burst_size_width + 1, initval=0,
1600+
prefix='counter')
15991601

16001602
self.write_counters.append(counter)
16011603

16021604
ready = make_condition(cond)
16031605

16041606
ack = vtypes.Ands(self.waddr.awready, self.waddr.awvalid,
16051607
vtypes.Not(self.wresp.bvalid))
1606-
addr = self.m.TmpReg(self.addrwidth, initval=0)
1607-
valid = self.m.TmpReg(initval=0)
1608+
addr = self.m.TmpReg(self.addrwidth, initval=0, prefix='addr')
1609+
valid = self.m.TmpReg(initval=0, prefix='valid')
16081610

1609-
prev_awvalid = self.m.TmpReg(initval=0)
1611+
prev_awvalid = self.m.TmpReg(initval=0, prefix='prev_awvalid')
16101612
self.seq(
16111613
prev_awvalid(self.waddr.awvalid)
16121614
)
@@ -1676,9 +1678,9 @@ def pull_write_dataflow(self, counter=None, cond=None):
16761678
if counter is None:
16771679
counter = self.write_counters[-1]
16781680

1679-
data_ready = self.m.TmpWire()
1680-
mask_ready = self.m.TmpWire()
1681-
last_ready = self.m.TmpWire()
1681+
data_ready = self.m.TmpWire(prefix='data_ready')
1682+
mask_ready = self.m.TmpWire(prefix='mask_ready')
1683+
last_ready = self.m.TmpWire(prefix='last_ready')
16821684
data_ready.assign(1)
16831685
mask_ready.assign(1)
16841686
last_ready.assign(1)
@@ -1725,17 +1727,17 @@ def pull_read_request_counter(self, cond=None, counter=None):
17251727
raise TypeError("counter must be Reg or None.")
17261728

17271729
if counter is None:
1728-
counter = self.m.TmpReg(self.burst_size_width + 1, initval=0)
1730+
counter = self.m.TmpReg(self.burst_size_width + 1, initval=0, prefix='counter')
17291731

17301732
self.read_counters.append(counter)
17311733

17321734
ready = make_condition(cond)
17331735

17341736
ack = vtypes.Ands(self.raddr.arready, self.raddr.arvalid)
1735-
addr = self.m.TmpReg(self.addrwidth, initval=0)
1736-
valid = self.m.TmpReg(initval=0)
1737+
addr = self.m.TmpReg(self.addrwidth, initval=0, prefix='addr')
1738+
valid = self.m.TmpReg(initval=0, prefix='valid')
17371739

1738-
prev_arvalid = self.m.TmpReg(initval=0)
1740+
prev_arvalid = self.m.TmpReg(initval=0, prefix='prev_arvalid')
17391741
self.seq(
17401742
prev_arvalid(self.raddr.arvalid)
17411743
)
@@ -2082,15 +2084,15 @@ def pull_request(self, cond):
20822084
write_ack = vtypes.Ands(self.waddr.awready, self.waddr.awvalid,
20832085
vtypes.Not(self.wresp.bvalid))
20842086
read_ack = vtypes.Ands(self.raddr.arready, self.raddr.arvalid)
2085-
addr = self.m.TmpReg(self.addrwidth, initval=0)
2086-
writevalid = self.m.TmpReg(initval=0)
2087-
readvalid = self.m.TmpReg(initval=0)
2087+
addr = self.m.TmpReg(self.addrwidth, initval=0, prefix='addr')
2088+
writevalid = self.m.TmpReg(initval=0, prefix='writevalid')
2089+
readvalid = self.m.TmpReg(initval=0, prefix='readvalid')
20882090

2089-
prev_awvalid = self.m.TmpReg(initval=0)
2091+
prev_awvalid = self.m.TmpReg(initval=0, prefix='prev_awvalid')
20902092
self.seq(
20912093
prev_awvalid(self.waddr.awvalid)
20922094
)
2093-
prev_arvalid = self.m.TmpReg(initval=0)
2095+
prev_arvalid = self.m.TmpReg(initval=0, prefix='prev_arvalid')
20942096
self.seq(
20952097
prev_arvalid(self.raddr.arvalid)
20962098
)
@@ -2137,10 +2139,10 @@ def pull_write_request(self, cond=None):
21372139

21382140
ack = vtypes.Ands(self.waddr.awready, self.waddr.awvalid,
21392141
vtypes.Not(self.wresp.bvalid))
2140-
addr = self.m.TmpReg(self.addrwidth, initval=0)
2141-
valid = self.m.TmpReg(initval=0)
2142+
addr = self.m.TmpReg(self.addrwidth, initval=0, prefix='addr')
2143+
valid = self.m.TmpReg(initval=0, prefix='valid')
21422144

2143-
prev_awvalid = self.m.TmpReg(initval=0)
2145+
prev_awvalid = self.m.TmpReg(initval=0, prefix='prev_awvalid')
21442146
self.seq(
21452147
prev_awvalid(self.waddr.awvalid)
21462148
)
@@ -2200,10 +2202,10 @@ def pull_read_request(self, cond=None):
22002202
ready = make_condition(cond)
22012203

22022204
ack = vtypes.Ands(self.raddr.arready, self.raddr.arvalid)
2203-
addr = self.m.TmpReg(self.addrwidth, initval=0)
2204-
valid = self.m.TmpReg(initval=0)
2205+
addr = self.m.TmpReg(self.addrwidth, initval=0, prefix='addr')
2206+
valid = self.m.TmpReg(initval=0, prefix='valid')
22052207

2206-
prev_arvalid = self.m.TmpReg(initval=0)
2208+
prev_arvalid = self.m.TmpReg(initval=0, prefix='prev_arvalid')
22072209
self.seq(
22082210
prev_arvalid(self.raddr.arvalid)
22092211
)
@@ -2377,11 +2379,13 @@ def read_dataflow(self, cond=None, point=0, signed=True):
23772379
"""
23782380
@return data, last, _id, user, dest, done
23792381
"""
2380-
data_ready = self.m.TmpWire()
2381-
last_ready = self.m.TmpWire()
2382-
id_ready = self.m.TmpWire()
2383-
user_ready = self.m.TmpWire()
2384-
dest_ready = self.m.TmpWire()
2382+
2383+
# ???
2384+
data_ready = self.m.TmpWire(prefix='data_ready')
2385+
last_ready = self.m.TmpWire(prefix='last_ready')
2386+
id_ready = self.m.TmpWire(prefix='id_ready')
2387+
user_ready = self.m.TmpWire(prefix='user_ready')
2388+
dest_ready = self.m.TmpWire(prefix='dest_ready')
23852389
data_ready.assign(1)
23862390
id_ready.assign(1)
23872391
last_ready.assign(1)
@@ -3076,7 +3080,7 @@ def read(self, fsm, addr):
30763080
""" intrinsic for thread """
30773081

30783082
cond = fsm.state == fsm.current
3079-
rdata = self.m.TmpReg(self.mem_datawidth, initval=0, signed=True)
3083+
rdata = self.m.TmpReg(self.mem_datawidth, initval=0, signed=True, prefix='rdata')
30803084
num_bytes = self.mem_datawidth // 8
30813085

30823086
fsm.If(cond)(
@@ -3093,7 +3097,7 @@ def write(self, fsm, addr, wdata):
30933097
cond = fsm.state == fsm.current
30943098
num_bytes = self.mem_datawidth // 8
30953099

3096-
wdata_wire = self.m.TmpWire(self.mem_datawidth)
3100+
wdata_wire = self.m.TmpWire(self.mem_datawidth, prefix='wdata_wire')
30973101
wdata_wire.assign(wdata)
30983102

30993103
for i in range(num_bytes):
@@ -3109,7 +3113,7 @@ def read_word(self, fsm, word_index, byte_offset, bits=8):
31093113
""" intrinsic method word-indexed read """
31103114

31113115
cond = fsm.state == fsm.current
3112-
rdata = self.m.TmpReg(bits, initval=0, signed=True)
3116+
rdata = self.m.TmpReg(bits, initval=0, signed=True, prefix='rdata')
31133117
num_bytes = int(math.ceil(bits / 8))
31143118
addr = vtypes.Add(byte_offset,
31153119
vtypes.Div(vtypes.Mul(word_index, bits), 8))
@@ -3129,27 +3133,27 @@ def write_word(self, fsm, word_index, byte_offset, wdata, bits=8):
31293133
""" intrinsic method word-indexed write """
31303134

31313135
cond = fsm.state == fsm.current
3132-
rdata = self.m.TmpReg(bits, initval=0, signed=True)
3136+
rdata = self.m.TmpReg(bits, initval=0, signed=True, prefix='rdata')
31333137
num_bytes = int(math.ceil(bits / 8))
31343138
addr = vtypes.Add(byte_offset,
31353139
vtypes.Div(vtypes.Mul(word_index, bits), 8))
31363140
shift = word_index * bits % 8
31373141

3138-
wdata_wire = self.m.TmpWire(bits)
3142+
wdata_wire = self.m.TmpWire(bits, prefix='wdata_wire')
31393143
wdata_wire.assign(wdata)
31403144
mem_data = vtypes.Cat(*reversed([self.mem[addr + i]
31413145
for i in range(num_bytes)]))
3142-
mem_data_wire = self.m.TmpWire(8 * num_bytes)
3146+
mem_data_wire = self.m.TmpWire(8 * num_bytes, prefix='mem_data_wire')
31433147
mem_data_wire.assign(mem_data)
31443148

3145-
inv_mask = self.m.TmpWire(8 * num_bytes)
3149+
inv_mask = self.m.TmpWire(8 * num_bytes, prefix='inv_mask')
31463150
inv_mask.assign(vtypes.Repeat(vtypes.Int(1, 1), bits) << shift)
3147-
mask = self.m.TmpWire(8 * num_bytes)
3151+
mask = self.m.TmpWire(8 * num_bytes, prefix='mask')
31483152
mask.assign(vtypes.Unot(inv_mask))
31493153

31503154
raw_data = vtypes.Or(wdata_wire << shift,
31513155
vtypes.And(mem_data_wire, mask))
3152-
raw_data_wire = self.m.TmpWire(8 * num_bytes)
3156+
raw_data_wire = self.m.TmpWire(8 * num_bytes, prefix='raw_data_wire')
31533157
raw_data_wire.assign(raw_data)
31543158

31553159
for i in range(num_bytes):

0 commit comments

Comments
 (0)